US-20260128091-A1 - STATIC RANDOM ACCESS MEMORY BIT-CELL WITH COMPACT SIZE THAT SUPPORTS BIT-WRITE-MASK FEATURE AND HALF-SELECTION-FREE FEATURE

US20260128091A1US 20260128091 A1US20260128091 A1US 20260128091A1US-20260128091-A1

Abstract

A static random access memory (SRAM) bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors form a first inverter. The third and fourth transistors form a second inverter. The first inverter and the second inverter are cross-coupled. The write driver circuit is coupled to one reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to connection terminals of the first transistor and the third transistor. The second transistor circuit is coupled between the write driver circuit and another reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a word line.

Inventors

Tzu-Hsien YANG
Yi-Te Chiu

Assignees

MEDIATEK INC.

Dates

Publication Date: 20260507
Application Date: 20251030

Claims (20)

1 . A static random access memory (SRAM) bit-cell comprising: a cross-coupled latch circuit, comprising: a first transistor, having a control terminal, a first connection terminal, and a second connection terminal; a second transistor, having a control terminal coupled to the control terminal of the first transistor, a first connection coupled to the first terminal of the first transistor, and a second terminal coupled to a first reference voltage; a third transistor, having a control terminal coupled to the first terminal of the first transistor, a first connection terminal coupled to the control terminal of the first transistor, and a second connection terminal; and a fourth transistor, having a control terminal coupled to the control terminal of the third transistor, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal coupled to the first reference voltage; a write driver circuit, coupled to a second reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit; a first transistor circuit, coupled to the second connection terminal of the first transistor and the second connection terminal of the third transistor; and a second transistor circuit, coupled between the write driver circuit and the first reference voltage, wherein both of the first transistor circuit and the second transistor are controlled by a first word line.
2 . The SRAM bit-cell of claim 1 , wherein the write driver circuit comprises: a fifth transistor, having a control terminal coupled to a first write bit line of the write bit line pair, a first connection terminal coupled to the second connection terminal of the first transistor, and a second connection terminal coupled to the second reference voltage; a sixth transistor, having a control terminal coupled to the first write bit line, a first connection terminal coupled to the first connection terminal of the first transistor, and a second connection terminal coupled to the second transistor circuit; a seventh transistor, having a control terminal coupled to a second write bit line of the write bit line pair, a first connection terminal coupled to the second connection terminal of the third transistor, and a second connection terminal coupled to the second reference voltage; and an eighth transistor, having a control terminal coupled to the second write bit line, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal coupled to the second transistor circuit.
3 . The SRAM bit-cell of claim 2 , wherein the first transistor circuit comprises: a ninth transistor, having a control terminal coupled to the first word line, and two connection terminals coupled to the second connection terminal of the first transistor and the second connection terminal of the third transistor, respectively.
4 . The SRAM bit-cell of claim 2 , wherein the first transistor circuit comprises: a ninth transistor, having a control terminal coupled to the first word line, a first connection terminal coupled to the second connection terminal of the first transistor, and a second connection terminal coupled to the second reference voltage; and a tenth transistor, having a control terminal coupled to the first word line, a first connection terminal coupled to the second connection terminal of the third transistor, and a second connection terminal coupled to the second reference voltage.
5 . The SRAM bit-cell of claim 2 , wherein the second transistor circuit comprises: a ninth transistor, having a control terminal coupled to the first word line, a first connection terminal coupled to the second connection terminal of the sixth transistor and the second connection terminal of the eighth transistor, and a second connection terminal coupled to the first reference voltage.
6 . The SRAM bit-cell of claim 2 , wherein the second transistor circuit comprises: a ninth transistor, having a control terminal coupled to the first word line, a first connection terminal coupled to the second connection terminal of the sixth transistor, and a second connection terminal coupled to the first reference voltage; and a tenth transistor, having a control terminal coupled to the first word line, a first connection terminal coupled to the second connection terminal of the eighth transistor, and a second connection terminal coupled to the first reference voltage.
7 . The SRAM bit-cell of claim 1 , further comprising: a read buffer circuit, coupled between the first connection terminal of the third transistor and a read bit line.
8 . The SRAM bit-cell of claim 7 , wherein the first word line is a write word line, and the read buffer circuit is controlled by a second word line being a read word line.
9 . The SRAM bit-cell of claim 7 , wherein the read buffer circuit is controlled by the first word line.
10 . The SRAM bit-cell of claim 7 , wherein the read buffer circuit comprises: a fifth transistor, having a control terminal coupled to the first connection terminal of the third transistor, a first connection terminal, and a second connection terminal coupled to one of the first reference voltage and the second reference voltage; and a sixth transistor, having a control terminal, a first connection terminal coupled to the read bit line, and a second connection terminal coupled to the first connection terminal of the fifth transistor.
11 . The SRAM bit-cell of claim 7 , wherein the read buffer circuit is a complementary metal-oxide-semiconductor (CMOS) circuit.
12 . The SRAM bit-cell of claim 7 , wherein the read buffer circuit is a pass gate.
13 . The SRAM bit-cell of claim 7 , wherein the read buffer circuit is a combinational logic.
14 . The SRAM bit-cell of claim 1 , wherein the first reference voltage is lower than the second reference voltage.
15 . The SRAM bit-cell of claim 1 , wherein the first reference voltage is higher than the second reference voltage.
16 . The SRAM bit-cell of claim 1 , wherein the SRAM bit-cell located at a selected row and an unselected column, and the cross-coupled latch circuit operates to keep its stored bit unchanged.
17 . The SRAM bit-cell of claim 1 , wherein the SRAM bit-cell is located at an unselected row and a selected column, and the cross-coupled latch circuit operates to keep its stored bit unchanged.
18 . The SRAM bit-cell of claim 1 , wherein the SRAM bit-cell is a bit-write-masked SRAM bit-cell located at a selected column and a selected column, and the cross-coupled latch circuit operates to keep its stored bit unchanged.
19 . A 12-transistor (12T) two-port static random access memory (SRAM) bit-cell comprising: a first transistor, having a control terminal, a first connection terminal, and a second connection terminal; a second transistor, having a control terminal coupled to the control terminal of the first transistor, a first connection coupled to the first terminal of the first transistor, and a second terminal coupled to a first reference voltage; a third transistor, having a control terminal coupled to the first terminal of the first transistor, a first connection terminal coupled to the control terminal of the first transistor, and a second connection terminal; a fourth transistor, having a control terminal coupled to the control terminal of the third transistor, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal coupled to the first reference voltage; a fifth transistor, having a control terminal coupled to a first write bit line of a write bit line pair, a first connection terminal coupled to the second connection terminal of the first transistor, and a second connection terminal coupled to a second reference voltage; a sixth transistor, having a control terminal coupled to the first write bit line, a first connection terminal coupled to the first connection terminal of the first transistor, and a second connection terminal; a seventh transistor, having a control terminal coupled to a second write bit line of the write bit line pair, a first connection terminal coupled to the second connection terminal of the third transistor, and a second connection terminal coupled to the second reference voltage; an eighth transistor, having a control terminal coupled to the second write bit line, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal; a ninth transistor, having a control terminal coupled to a write word line, and two connection terminals coupled to the second connection terminal of the first transistor and the second connection terminal of the third transistor, respectively; a tenth transistor, having a control terminal coupled to the write word line, a first connection terminal coupled to the second connection terminal of the sixth transistor and the second connection terminal of the eighth transistor, and a second connection terminal coupled to the first reference voltage; an eleventh transistor, having a control terminal coupled to the first connection terminal of the third transistor, a first connection terminal, and a second connection terminal coupled to one of the first reference voltage and the second reference voltage; and a twelfth transistor, having a control terminal coupled to a read word line, a first connection terminal coupled to a read bit line, and a second connection terminal coupled to the first connection terminal of the eleventh transistor.
20 . The 12T two-port SRAM bit-cell of claim 19 , wherein a layout of the 12T SRAM bit-cell defines that: the seventh transistor, the ninth transistor, the first transistor, a first dummy transistor, a second dummy transistor, the third transistor, a third dummy transistor, and the fifth transistor are at a first row; a fourth dummy transistor, the tenth transistor, the second transistor, the sixth transistor, the eighth transistor, the fourth transistor, the eleventh transistor, and the twelfth transistor are at a second row adjacent to the first row; the seventh transistor and the fourth dummy transistor are at a first column; the ninth transistor and the tenth transistor are at a second column between the first column and a third column; the first transistor and the second transistor are at the third column between the second column and a fourth column; the first dummy transistor and the sixth transistor are at the fourth column between the third column and a fifth column; the second dummy transistor and the eighth transistor are at the fifth column between the fourth column and a sixth column; the third transistor and the fourth transistor are at the sixth column between the fifth column and a seventh column; the third dummy transistor and the eleventh transistor are at the seventh column between the sixth column and an eighth column; and the fifth transistor and the twelfth transistor are at the eighth column.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/714,868, filed on Nov. 1, 2024. The content of the application is incorporated herein by reference. BACKGROUND The present invention relates to a static random access memory (SRAM) design, and more particularly, to an SRAM bit-cell with a compact size that supports a bit-write-mask feature and a half-selection-free feature. The digital two-port SRAM is designed for ultra-low voltage operation and is suitable for small to medium array sizes, offering a more compact solution compared to traditional 6T-based SRAMs. It ensures a contention-free write operation by breaking a feedback loop between a cross-coupled latch (which consists of cross-coupled inverters) during data writing. Additionally, a read buffer is employed for data reading to eliminate any disturbances on bit-cell storage nodes, enabling ultra-low voltage operation. Despite its advantages, digital two-port SRAM faces the challenge of the half-selection issue, requiring a read-modify-write operation for a 12T SRAM bit-cell, which impacts performance. Thus, there is a need for an innovative SRAM bit-cell design which can address the half-selection issue and support the bit-write mask feature, without compromising the bit-density. SUMMARY One of the objectives of the claimed invention is to provide an SRAM bit-cell with a compact size that supports a bit-write-mask feature and a half-selection-free feature. According to a first aspect of the present invention, an exemplary SRAM bit-cell is disclosed. The exemplary SRAM bit-cell includes a cross-coupled latch circuit, a write driver circuit, a first transistor circuit, and a second transistor circuit. The cross-coupled latch circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor has a control terminal, a first connection terminal, and a second connection terminal. The second transistor has a control terminal coupled to the control terminal of the first transistor, a first connection coupled to the first terminal of the first transistor, and a second terminal coupled to a first reference voltage. The third transistor has a control terminal coupled to the first terminal of the first transistor, a first connection terminal coupled to the control terminal of the first transistor, and a second connection terminal. The fourth transistor has a control terminal coupled to the control terminal of the third transistor, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal coupled to the first reference voltage. The write driver circuit is coupled to a second reference voltage and a write bit line pair, and configured to write a data input into the cross-coupled latch circuit. The first transistor circuit is coupled to the second connection terminal of the first transistor and the second connection terminal of the third transistor. The second transistor circuit is coupled between the write driver circuit and the first reference voltage. Both of the first transistor circuit and the second transistor are controlled by a first word line. According to a second aspect of the present invention, an exemplary 12T two-port SRAM bit-cell is disclosed. The exemplary 12T two-port SRAM bit-cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The first transistor has a control terminal, a first connection terminal, and a second connection terminal. The second transistor has a control terminal coupled to the control terminal of the first transistor, a first connection coupled to the first terminal of the first transistor, and a second terminal coupled to a first reference voltage. The third transistor has a control terminal coupled to the first terminal of the first transistor, a first connection terminal coupled to the control terminal of the first transistor, and a second connection terminal. The fourth transistor has a control terminal coupled to the control terminal of the third transistor, a first connection terminal coupled to the first connection terminal of the third transistor, and a second connection terminal coupled to the first reference voltage. The fifth transistor has a control terminal coupled to a first write bit line of a write bit line pair, a first connection terminal coupled to the second connection terminal of the first transistor, and a second connection terminal coupled to a second reference voltage. The sixth transistor has a control terminal coupled to the first write bit line, a first connection terminal coupled to the first connection terminal of the first transistor, and a second connection terminal. The seventh transistor has a cont