US-20260128094-A1 - THREE-DIMENSIONAL MEMORY DEVICE WITH INTEGRATED LINE-AND-VIA STRUCTURES AND METHODS FOR FORMING THE SAME

US20260128094A1US 20260128094 A1US20260128094 A1US 20260128094A1US-20260128094-A1

Abstract

A device structure includes a vertical stack of insulating layers, a retro-stepped dielectric material portion overlying the vertical stack of insulating layers, and integrated line-and-via structures embedded within the vertical stack and the retro-stepped dielectric material portion. Each of the integrated line-and-via structures includes a respective horizontally-extending portion that forms a respective electrically conductive layer, and further includes a respective layer-connection via structure that vertically extends upward from the respective horizontally-extending portion through retro-stepped dielectric material portion. Memory openings vertically extend through the alternating stack, and memory opening fill structures are located in the memory openings.

Inventors

Koichi Matsuno
Kota Funayama

Assignees

SanDisk Technologies, Inc.

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A device structure, comprising: a vertical stack of insulating layers that are vertically spaced apart from each other and having different lateral extents in a staircase region; a retro-stepped dielectric material portion overlying the vertical stack of insulating layers in the staircase region; integrated line-and-via structures embedded within the vertical stack and the retro-stepped dielectric material portion, wherein each of the integrated line-and-via structures comprises a respective horizontally-extending portion that comprises a respective electrically conductive layer that is located between a respective vertically neighboring pair of the insulating layers, and further comprises a respective layer-connection via structure that vertically extends upward from the respective horizontally-extending portion through retro-stepped dielectric material portion and vertically extends downward through a respective underlying subset of the insulating layers, wherein a set of the electrically conductive layers of the integrated line-and-via structures and the vertical stack of insulating layers are interlaced to provide an alternating stack of the insulating layers and the electrically conductive layers; memory openings vertically extending through the alternating stack; and memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and a vertical semiconductor channel.
2 . The device structure of claim 1 , wherein each of the integrated line-and-via structures comprises a respective metallic barrier liner that comprises: a horizontally-extending metallic barrier liner portion that constitutes a peripheral portion of the respective electrically conductive layer; and vertically-extending tubular metallic barrier liner portions that comprise outer portions of the respective layer-connection via structure.
3 . The device structure of claim 2 , wherein each of the integrated line-and-via structures further comprises a respective metal fill material portion that comprises: a horizontally-extending metal fill material portion that is embedded within the a horizontally-extending metallic barrier liner portion of the respective electrically conductive layer; and a vertically-extending tubular metal fill material portion that comprises an inner portion of the respective layer-connection via structure.
4 . The device structure of claim 3 , wherein: the respective metal fill material portion consists essentially of an elemental metal; and the respective metallic barrier liner consists essentially of a conductive metallic nitride material.
5 . The device structure of claim 2 , wherein each of the integrated line-and-via structures is spaced from a combination of the vertical stack of insulating layers and the retro-stepped dielectric material portion by a respective outer blocking dielectric layer.
6 . The device structure of claim 5 , wherein each of the memory opening fill structures is contacted by and is laterally surrounded by a respective set of tubular segments of the outer blocking dielectric layers.
7 . The device structure of claim 1 , wherein, within each of the integrated line-and-via structures, the respective layer-connection via structure comprises a respective vertically-extending tubular portion.
8 . The device structure of claim 7 , wherein, within each of the integrated line-and-via structures, the respective layer-connection via structure laterally surrounds a respective dielectric via core structure.
9 . The device structure of claim 7 , wherein, within each of the integrated line-and-via structures, the respective layer-connection via structure further comprises a respective bottom cap portion that underlies and is adjoined to a bottom periphery of the respective vertically-extending tubular portion.
10 . The device structure of claim 1 , further comprising a contact-level dielectric layer that overlies the alternating stack and the retro-stepped dielectric material portion, wherein each of the integrated line-and-via structures comprises a respective horizontal tab portion that extends over and contacts a top surface of the contact-level dielectric layer.
11 . The device structure of claim 10 , further comprising: a via-level dielectric layer that overlies the contact-level dielectric layer; and drain contact via structures vertically extending through the via-level dielectric layer and the contact-level dielectric layer and contacting a respective one of the memory opening fill structures.
12 . The device structure of claim 11 , further comprising tab-contact via structures vertically extending through an upper portion of the via-level dielectric layer and contacting a respective one of the tab portions of the integrated line-and-via structures.
13 . The device structure of claim 12 , wherein the tab-contact via structures and the drain contact via structures comprise a same set of at least one conductive material, and have top surfaces located within a horizontal plane including a top surface of the via-level dielectric layer.
14 . The device structure of claim 1 , wherein each of the electrically conductive layers of the integrated line-and-via structures comprises a respective first horizontally-extending electrically conductive portion having a first thickness and a respective second horizontally-extending electrically conductive portion having a second thickness that is greater than the first thickness.
15 . The device structure of claim 14 , wherein, for each of the electrically conductive layers of the integrated line-and-via structures, an outer sidewall of the respective second horizontally-extending electrically conductive portion is equidistant from an outer sidewall of the respective layer-connection via structure of a respective one of the integrated line-and-via structures.
16 . A method of forming a device structure, comprising: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming stepped surfaces by patterning the alternating stack in a staircase region; forming a retro-stepped dielectric material portion over the stepped surfaces; forming a contact via cavity through the retro-stepped dielectric material portion and a subset of the sacrificial material layers within the alternating stack, wherein the subset of the sacrificial material layers comprises a first sacrificial material layer which is a topmost sacrificial material layer of the subset of the sacrificial material layers and further comprises second sacrificial material layers that underlie the first sacrificial material layer; replacing annular portions of the second sacrificial material layers around the contact via cavity with annular dielectric spacers; forming lateral recesses by removing the sacrificial material layers selectively to the insulating layers, the retro-stepped dielectric material portion, and the annular dielectric spacers, wherein one of the lateral recesses that is connected directly to the contact via cavity comprises a first lateral recess; and forming a first integrated line-and-via structure within a continuous volume including volumes of the contact via cavity and the first lateral recess at the same time, wherein the first integrated line-and-via structure comprises a first electrically conductive layer that is formed within the first lateral recess, and further comprises a first layer-connection via structure that is formed within the contact via cavity.
17 . The method of claim 16 , further comprising: forming additional contact via cavities through the retro-stepped dielectric material portion and portions of the alternating stack that underlie the retro-stepped dielectric material portion, wherein, for each selected sacrificial material layer of the sacrificial material layers, a respective one of the contact via cavity or the additional contact via cavities vertically extends through the selected sacrificial material layer; and depositing at least one electrically conductive material in the lateral recesses and in peripheral portions of the contact via cavity and the additional contact via cavities, wherein each of the contact via cavity and the additional contact via cavities comprises a respective cylindrical peripheral region that is filled with a respective portion of the at least one electrically conductive material.
18 . The method of claim 17 , further comprising: performing a selective etch process that removes the sacrificial material layers selectively to the insulating layers employing at least the contact via cavity and the additional contact via cavities as conduits for transporting an isotropic etchant of the selective etch process; and performing a conformal deposition process that deposits at least one electrically conductive material in each of the lateral recesses and in the cylindrical peripheral regions of the contact via cavity and the additional contact via cavities employing at least the contact via cavity and the additional contact via cavities as conduits for transporting a reactant gas for depositing the at least one electrically conductive material.
19 . The method of claim 18 , further comprising forming lateral isolation trenches through the alternating stack and the retro-stepped dielectric material portion, wherein: the lateral isolation trenches are laterally spaced from each of the contact via cavity and the additional contact via cavities; the lateral isolation trenches are used as additional conduits for transporting the isotropic etchant of the selective etch process; and the lateral isolation trenches are used as additional conduits for transporting the reactant gas for depositing the at least one electrically conductive material.
20 . The method of claim 16 , wherein: horizontal surface segments of the sacrificial material layers are physically exposed after formation of the stepped surfaces; the method further comprises locally thickening the sacrificial material layers by depositing a sacrificial material on the physically exposed horizontal surface segments of the sacrificial material layers after formation of the stepped surfaces; the retro-stepped dielectric material portion is formed after locally thickening the sacrificial material layers; and the first electrically conductive layer comprises a first horizontally-extending electrically conductive portion having a first thickness and a second horizontally-extending electrically conductive portion having a second thickness that is greater than the first thickness.

Description

FIELD The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including integrated line-and-via structures and methods for forming the same. BACKGROUND A three-dimensional memory device including three-dimensional vertical NAND strings having one bit per cell is disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. SUMMARY According to an aspect of the present disclosure, a device structure comprises: a vertical stack of insulating layers that are vertically spaced apart from each other and having different lateral extents in a staircase region; a retro-stepped dielectric material portion overlying the vertical stack of insulating layers in the staircase region; integrated line-and-via structures embedded within the vertical stack and the retro-stepped dielectric material portion, wherein each of the integrated line-and-via structures comprises a respective horizontally-extending portion that comprises a respective electrically conductive layer that is located between a respective vertically neighboring pair of the insulating layers, and further comprises a respective layer-connection via structure that vertically extends upward from the respective horizontally-extending portion through retro-stepped dielectric material portion and vertically extends downward through a respective underlying subset of the insulating layers, wherein a set of the electrically conductive layers of the integrated line-and-via structures and the vertical stack of insulating layers are interlaced to provide an alternating stack of the insulating layers and the electrically conductive layers; memory openings vertically extending through the alternating stack; and memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements and vertical semiconductor channel. According to another aspect of the present disclosure, a method of forming a device structure comprises: forming an alternating stack of insulating layers and sacrificial material layers over a substrate; forming stepped surfaces by patterning the alternating stack in a staircase region; forming a retro-stepped dielectric material portion over the stepped surfaces; forming a contact via cavity through the retro-stepped dielectric material portion and a subset of the sacrificial material layers within the alternating stack, wherein the subset of the sacrificial material layers comprises a first sacrificial material layer which is a topmost sacrificial material layer of the subset of the sacrificial material layers and further comprises second sacrificial material layers that underlie the first sacrificial material layer; replacing annular portions of the second sacrificial material layers around the contact via cavity with annular dielectric spacers; forming lateral recesses by removing the sacrificial material layers selectively to the insulating layers, the retro-stepped dielectric material portion, and the annular dielectric spacers, wherein one of the lateral recesses that is connected directly to the contact via cavity comprises a first lateral recess; and forming a first integrated line-and-via structure within a continuous volume including volumes of the contact via cavity and the first lateral recess at the same time, wherein the first integrated line-and-via structure comprises a first electrically conductive layer that is formed within the first lateral recess, and further comprises a first layer-connection via structure that is formed within the contact via cavity. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a plan view of a configuration of an exemplary semiconductor die including multiple three-dimensional memory array regions according to an embodiment of the present disclosure. FIG. 1B is a schematic see-through top-down view of region M1 of FIG. 1A. FIG. 1C is a schematic vertical cross-sectional view of a region of the exemplary semiconductor die along the vertical plane C-C′ of FIG. 1B. The vertical plane E-E′ is the cut plane of the schematic vertical cross-sectional view of FIG. 1E. FIG. 1D is a schematic vertical cross-sectional view of a region of the exemplary semiconductor die along the vertical plane D-D′ of FIG. 1B. FIG. 1E is a schematic vertical cross-sectional view of a region of the exemplary semiconductor die along the vertical plane E-E′ of FIG. 1B. The vertical plane C-C′ is the cut plane of the schematic vertical cross-sectional view of FIG. 1C. FIG. 1F is a vertical cross-sectional view of a region of the exemplary semiconductor die around a memory opening fill structure. FIG. 2A is a schematic vertical cross-sectional view of an exemplary structure for forming a semiconductor die after formation of a vertically alternating sequence of f