US-20260128095-A1 - REFERENCE SIGNAL GENERATION IN THREE-DIMENSIONAL NOR MEMORY ARRAY OF THIN-FILM FERROELECTRIC MEMORY TRANSISTORS

Abstract

A memory structure including three-dimensional NOR memory strings and method of operation is disclosed. In some embodiments, the memory device implements partial polarization to provide a reference signal for read operation. The reference signal realizes a third logical state distinguishable from the first and second logical stages in the ferroelectric memory transistor, such as associated with the program and erase states. In another embodiment, the memory device provides a reference signal for read operation by averaging a first signal associated with a program state and a second signal associated with an erased state of the ferroelectric memory transistor. In some embodiments, the memory device implements one or more partial polarization states to provide a multi-level memory cell with more than one logical bit stored in each memory cell.

Inventors

• Eli Harari
• Masahiro Yoshihara
• Michael McCarthy

Assignees

• SUNRISE MEMORY CORPORATION

Dates

Publication Date

20260507

Application Date

20251219

Claims (20)

1. 1 . A memory device, comprising: an array of memory strings, each memory string including thin-film ferroelectric memory transistors having drain terminals coupled to a common bit line, source terminals coupled to a common source line, and gate terminals coupled to respective word lines, ferroelectric memory transistors across multiple memory strings that are vertically aligned in the array being coupled to a common word line, each ferroelectric memory transistor including a ferroelectric gate dielectric layer that is polarizable in response to application of bias voltages to the drain, source and gate terminals, wherein the ferroelectric memory transistors are driven by a first set of bias voltages to provide a first polarization state in the ferroelectric gate dielectric layer, the first polarization state being associated with a first threshold voltage value, and further driven by a second set of bias voltages to provide a second polarization state in the ferroelectric gate dielectric layer, the second polarization state being associated with a second threshold voltage value, the second threshold voltage value being greater than the first threshold voltage value; and wherein a first ferroelectric memory transistor in the array is designated as a first reference memory transistor and a second ferroelectric memory transistor in the array is designated as a second reference memory transistor, the first reference memory transistor being driven by the first set of bias voltages to the first polarization state and the second reference memory transistor being driven by the second set of bias voltages to the second polarization state, bit line signals from the first and second reference memory transistors, indicative of respective first and second polarization states, are combined to generate a reference signal for reading the ferroelectric memory transistors to determine the logical state of the stored memory data.
2. 2 . The memory device of claim 1 , wherein bit line signals from the first and second reference memory transistors are coupled to a bit line selector and in response to a bit line select signal, the bit line selector selects and activates both bit line signals from the first and second reference memory transistors to generate an average bit line signal, the reference signal being indicative of the average bit line signal.
3. 3 . The memory device of claim 1 , further comprising a first plurality of ferroelectric memory transistors as a first plurality of reference memory transistors and a second plurality of ferroelectric memory transistors as second plurality of reference memory transistors, bit line signals from the first and second plurality of reference memory transistors, indicative of respective first and second polarization states, are combined to generate the reference signal.
4. 4 . The memory device of claim 3 , wherein bit line signals from the first and second plurality of reference memory transistors are coupled to a bit line selector and in response to a bit line select signal, the bit line selector selects and activates the bit line signals from the first and second plurality of reference memory transistors to generate an average bit line signal, the reference signal being indicative of the average bit line signal.
5. 5 . The memory device of claim 1 , wherein the first polarization state comprises a positive polarization state in the ferroelectric gate dielectric layer and the second polarization state comprises a negative polarization state in the ferroelectric gate dielectric layer.
6. 6 . The memory device of claim 5 , wherein the first polarization state is associated with memory data of a first logical state being stored in a respective ferroelectric memory transistor, the second polarization state is associated with memory data of a second logical state being stored in a respective ferroelectric memory transistor, and the reference signal is provided for reading from the other ferroelectric memory transistors to determine the logical state of the stored data.
7. 7 . The memory device of claim 5 , wherein the first set of bias voltages comprises a positive bias being applied to the gate terminal of the ferroelectric memory transistor relative to the drain and source terminals to induce the first polarization state in the ferroelectric gate dielectric layer and the second set of bias voltages comprises a negative bias being applied to the gate terminal of the ferroelectric memory transistor relative to the drain and source terminals to induce the second polarization state in the ferroelectric gate dielectric layer.
8. 8 . The memory device of claim 7 , wherein the second set of bias voltages comprises a positive bias being applied to the drain and source terminals of the ferroelectric memory transistor relative to the gate terminal to induce the second polarization state in the ferroelectric gate dielectric layer.
9. 9 . The memory device of claim 3 , wherein the array of memory strings comprises a three-dimensional array of memory strings, including memory strings arranged one on top of another in the vertical direction to form a memory stack and memory strings arranged in a row in a first horizontal direction to form a memory plane, the ferroelectric memory transistors being arranged in each memory string along a second horizontal direction, orthogonal to the first horizontal direction, ferroelectric memory transistors across the three-dimensional array of memory strings forming a memory slice provided in a plane in the vertical direction and the first horizontal direction.
10. 10 . The memory device of claim 9 , wherein one or more memory planes in the three-dimensional array of memory strings are designated as reference memory planes and the first and second plurality of reference memory transistors are provided in one or more reference memory planes.
11. 11 . The memory device of claim 9 , wherein one or more memory stacks in the three-dimensional array of memory strings are designated as reference memory stacks and the first and second plurality of reference memory transistors are provided in one or more reference memory stacks.
12. 12 . The memory device of claim 9 , wherein one or more memory slices in the three-dimensional array of memory strings are designated as reference memory slices and the first and second plurality of reference memory transistors are provided in one or more reference memory slices.
13. 13 . The memory device of claim 1 , wherein the common bit lines of the array of memory strings of ferroelectric memory transistors are coupled to a plurality of sense amplifiers, each sense amplifier receiving a bit line signal associated with a memory transistor being accessed to read the stored data and generating a sense amplifier output signal indicative of the stored data; and wherein the reference signal is provided to a reference sense amplifier to generate a read reference signal, the read reference signal being applied to latch the sense amplifier output signal generated by the sense amplifier connected to a bit line associated with a memory transistor being selected for access by a respective word line.
14. 14 . The memory device of claim 1 , wherein the common bit lines of the array of memory strings of ferroelectric memory transistors are coupled to a plurality of differential sense amplifiers, each differential sense amplifier receiving a bit line signal associated with a memory transistor being accessed and receiving a sense amplifier reference signal, each differential sense amplifier generating a sense amplifier output signal indicative of the stored data; and wherein the reference is provided to the plurality of differential sense amplifiers as the sense amplifier reference signal.
15. 15 . The memory device of claim 14 , wherein the reference signal is read from the first and second reference memory transistors and stored at the differential sense amplifiers for comparison with the bit line signals associated with the memory transistors being accessed.
16. 16 . The memory device of claim 1 , wherein two or more ferroelectric memory transistors in a first memory string are designated as the first and second reference memory transistors respectively and the common bit line of the first memory string is coupled to a first sense amplifier, wherein the first and second reference memory transistors on the first memory string are selected for access and provide the bit line signals to the first sense amplifier to generate the reference signal, the reference signal being stored at a first differential input terminal of the first sense amplifier, and wherein a third ferroelectric memory transistor on the first memory string is selected for access and provides a bit line signal to a second differential input terminal of the first sense amplifier, the first sense amplifier generating a sense amplifier output signal by comparing the bit line signal with the reference signal already stored at the first sense amplifier.
17. 17 . The memory device of claim 3 , wherein the first plurality of reference memory transistors has the same number of ferroelectric memory transistors as the second plurality of reference memory transistors.
18. 18 . The memory device of claim 17 , wherein the reference signal has a voltage value being halfway between the first threshold voltage value and the second threshold voltage value.
19. 19 . The memory device of claim 3 , wherein the first plurality of reference memory transistors has a different number of ferroelectric memory transistors as the second plurality of reference memory transistors.
20. 20 . The memory device of claim 19 , wherein the reference signal has a voltage value closer to the first threshold voltage value or closer to the second threshold voltage value than a voltage value halfway between the first threshold voltage value and the second threshold voltage value.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/651,510, entitled “Three-Dimensional NOR Memory Array of Thin-Film Ferroelectric Memory Transistors Implementing Partial Polarization,” filed Apr. 30, 2024, which claims priority to U.S. Provisional Patent Application No.63/501,124, entitled “Three-Dimensional NOR Memory Array of Thin-Film Ferroelectric Memory Transistors Implementing Partial Polarization for Reference Signal,” filed May 9, 2023, which applications are incorporated herein by reference in their entireties for all purposes. FIELD OF THE INVENTION The invention relates to semiconductor memory devices and methods of operation. More specifically, the present invention relates to a three-dimensional memory array of thin-film ferroelectric memory transistors implementing partial polarization to provide additional polarization states, which can be applied for use as a reference signal or as additional data bits. BACKGROUND OF THE INVENTION High density memory arrays, such as 3-dimensional arrays of NOR memory strings (“3-D NOR memory arrays”), have been disclosed in, for example, U.S. Pat. No. 10,121,553 (“the '553 patent”), entitled “Capacitive-Coupled Non-Volatile Thin-film Transistor NOR Strings in Three-Dimensional Arrays,” filed on Aug. 26, 2016, and issued on Nov. 6, 2018. The '553 patent disclosure is hereby incorporated by reference in its entirety for all purposes. In the '553 patent, storage or memory transistors are organized as 3-dimensional arrays of NOR memory strings formed above a planar surface of a semiconductor substrate. In the '553 patent, a NOR memory string includes numerous thin-film storage transistors that share a common bit line and a common source line. In one implementation, storage transistors in a NOR memory string are arranged along a direction (a “horizontal direction”) that is substantially parallel to the planar surface of the semiconductor substrate. In such a 3-dimensional array, the NOR memory strings are provided on multiple planes (e.g., 8 or 16 planes) above the semiconductor substrate, with the NOR memory strings on each plane arranged in rows and one or more columns along two orthogonal horizontal directions. Data is stored in a charge-trapping layer (e.g., a silicon oxide-silicon nitride-silicon oxide triple layer) in each storage transistor. Each storage transistor of a NOR memory string is read, programmed, or erased by suitably biasing its associated word line and the common bit line it shares with other storage transistors in the NOR memory string. In addition to providing high memory density and capacity, these 3-D NOR memory arrays may be operated to provide memory circuits at highly desirable speeds that rival conventional memory circuits of much lower circuit densities and significantly higher power dissipation, e.g., such as dynamic random-access memories (“DRAMs”). Furthermore, the memory circuits in the '553 patent are sometimes referred to as “quasi-volatile memory” or “QV memory.” Like those of a non-volatile memory (NVM), the memory cells of a QV memory each store a data bit as an electric charge in a charge storage material (e.g., ONO). Because of the nature of its charge-storage layer, a typical QV memory cell has a much longer data retention time than a DRAM cell and, hence, requires a lower refresh rate than the DRAM cell. For example, a typical DRAM system is designed to be refreshed every 64 milliseconds; a QV memory with a comparable effective access performance, however, may be refreshed every 10 minutes. The reduced refresh rate provides the QV memory great advantages in a lower power requirement, a reduced heat dissipation, and a higher memory availability which delivers a better host performance. Advances in electrically polarizable materials (“ferroelectric materials”), especially those that are being used in semiconductor manufacturing processes, suggest new potential applications in ferroelectric memory circuits. High density memory arrays implemented using 3-dimensional arrays of NOR memory strings of ferroelectric memory transistors have been disclosed in, for example, U.S. patent application Ser. No. 17/936,320, entitled “Memory Structure Including Three-Dimensional NOR Memory Strings Of Junctionless Ferroelectric Memory Transistors And Method Of Fabrication,” filed Sep. 28, 2022 (“the '320 application”). The '320 application is hereby incorporated by reference in its entirety for all purposes. The '320 application describes a memory structure that includes randomly accessible ferroelectric memory transistors organized as horizontal NOR memory strings. The ferroelectric memory transistors include a polarizable ferroelectric material as the gate dielectric layer. The NOR memory strings are formed over a semiconductor substrate in multiple scalable memory stacks of thin-film memory transistors. In some examples, the three-dimensional memory stacks are manufactured