US-20260128096-A1 - BIAS CIRCUIT FOR NON-VOLATILE MEMORY ARRAY IN A NEURAL NETWORK

Abstract

In one example, a system comprises an array of non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a word line terminal and a bit line terminal; and a row circuit to receive a row address and a bias voltage and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit, wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit.

Inventors

• Hoa Vu
• Hieu Van Tran
• Thuan Vu
• Stanley Hong
• Stephen Trinh

Assignees

• SILICON STORAGE TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20241220

Claims (20)

1. 1 . A system comprising: an array of non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a word line terminal and a bit line terminal; and a row circuit to receive a row address and a bias voltage and to output the bias voltage when the row address corresponds to a row of the array associated with the row circuit, wherein the bias voltage is provided to terminals of non-volatile memory cells in the row of the array associated with the row circuit.
2. 2 . The system of claim 1 , wherein the terminals are word line terminals.
3. 3 . The system of claim 1 , wherein the terminals are control gate terminals.
4. 4 . The system of claim 1 , wherein the row circuit receives the row address during a read operation of one or more non-volatile memory cells in the row of the array associated with the row circuit.
5. 5 . The system of claim 1 , wherein the row circuit receives the row address during a verify operation of one or more non-volatile memory cells in the row of the array associated with the row circuit.
6. 6 . The system of claim 1 , wherein the bias voltage is generated by a word line bias generation circuit.
7. 7 . The system of claim 6 , wherein the word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a select transistor comprising a first terminal coupled to the second terminal of the load, a gate, and a second terminal; a current source comprising a first terminal coupled to the second terminal of the select transistor and a second terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the second terminal of the select transistor, and an output coupled to the gate of the select transistor and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
8. 8 . The system of claim 7 , wherein the load comprises one or more resistors, capacitors, and transistors.
9. 9 . The system of claim 6 , wherein the word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a reference memory cell comprising a bit line terminal coupled to the second terminal of the load, a word line terminal, and a source line terminal; a select transistor comprising a first terminal coupled to the source line terminal of the reference memory cell, a gate coupled to a control signal, and a second terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the source line terminal of the reference memory cell, and an output coupled to the word line terminal of the reference memory cell and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
10. 10 . The system of claim 9 , wherein the load comprises one or more resistors, capacitors, and transistors.
11. 11 . The system of claim 6 , wherein the word line bias generation circuit comprises: a load comprising a first terminal coupled to a voltage source and a second terminal; a select transistor comprising a first terminal coupled to the second terminal of the load, a gate, and a second terminal; a reference memory cell comprising a bit line terminal coupled to the second terminal of the select transistor and a source line terminal coupled to ground; and an operational amplifier comprising a non-inverting input terminal coupled to a reference voltage, an inverting input terminal coupled to the bit line terminal of the reference memory cell, and an output coupled to the gate of the select transistor and to an output of the word line bias generation circuit, wherein the output of the word line bias generation circuit provides the bias voltage.
12. 12 . The system of claim 11 , wherein the load comprises one or more resistors, capacitors, and transistors.
13. 13 . A method comprising: receiving, by a row decoder coupled to an array of non-volatile memory cells arranged in rows and columns, a row address and a bias voltage; outputting, by the row decoder, the bias voltage when the row address corresponds to a row of the array associated with the row decoder; and applying, by the row decoder the bias voltage to terminals of non-volatile memory cells in the row of the array associated with the row decoder.
14. 14 . The method of claim 13 , wherein the terminals are word line terminals.
15. 15 . The method of claim 13 , wherein the terminals are control gate terminals.
16. 16 . The method of claim 15 , wherein the bias voltage causes voltages of drains of floating gate transistors of the non-volatile memory cells in the row of the array associated with the row decoder to be approximately constant as temperature, process, or power supply changes.
17. 17 . The method of claim 15 , wherein the bias voltage is generated by a replica bias circuit.
18. 18 . The method of claim 17 , wherein the replica bias circuit comprises a reference memory cell originated from a same process as non-volatile memory cells in the array.
19. 19 . A method comprising: applying a bias voltage to a terminal of a selected non-volatile memory cell; activating a transistor comprising a first terminal coupled to a bit line terminal of the selected non-volatile memory cell and a second terminal; and generating a voltage at the second terminal of the transistor indicating a value stored in the selected non-volatile memory cell.
20. 20 . The method of claim 19 , wherein the terminal of the selected non-volatile memory cell is a word line terminal.

Description

PRIORITY CLAIM This application claims priority to U.S. Provisional Patent Application No. 63/716,175, filed on Nov. 4, 2024, and titled “Bias Circuit for Non-Volatile Memory Array in Neural Network,” which is incorporated by reference herein. FIELD OF THE INVENTION Numerous examples are disclosed of a bias circuit for a non-volatile memory array in a neural network. BACKGROUND OF THE INVENTION Artificial neural networks mimic biological neural networks (the central nervous systems of animals, in particular the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are generally unknown. Artificial neural networks generally include layers of interconnected “neurons” which exchange messages between each other. FIG. 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses. One of the major challenges in the development of artificial neural networks for high-performance information processing is a lack of adequate hardware technology. Indeed, practical neural networks rely on a very large number of synapses, enabling high connectivity between neurons, i.e., a very high computational parallelism. In principle, such complexity can be achieved with digital supercomputers or graphics processing unit clusters. However, in addition to high cost, these approaches also suffer from mediocre energy efficiency as compared to biological networks, which consume much less energy primarily because they perform low-precision analog computation. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses have been too bulky given the high number of neurons and synapses. Applicant previously disclosed an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as the synapses in U.S. Patent Application Publication 2017/0337466A1, which is incorporated by reference. The non-volatile memory arrays operate as an analog neural memory and comprise non-volatile memory cells arranged in rows and columns. The neural network includes a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight values to generate the first plurality of outputs. Non-Volatile Memory Cells Non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 (“the '130 patent”), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between. Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion that extends up and over the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. Bitline 24 is coupled to drain region 16. Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling. Memory cell 210 is programmed by source side injection (SSI) with hot electrons (where electrons are placed