US-20260128097-A1 - Memory Circuitry And Methods Used In Forming Memory Circuitry

Abstract

Memory circuitry comprises strings of NAND memory cells and horizontal high voltage transistors that are operatively electrically coupled with the vertical strings. The horizontal high voltage transistors individually comprise two horizontally-spaced regions having a vertical fin extending horizontally there-between. Two source/drain regions are individually in one of the two horizontally-spaced regions and individually comprise a highest-doped region that is horizontally spaced from the vertical fin and a lightly-doped region that is beneath and laterally aside the highest-doped region between the highest-doped region and the vertical fin (with the lightly-doped region being horizontally spaced from the vertical fin by an intermediate region of one of the two horizontally-spaced regions). A channel region is horizontally between the two source/drain regions and is in the vertical fin and in each intermediate region. A conductive gate is operatively over a top surface and opposing lateral side surfaces of the vertical fin and over a top surface of each intermediate region. Methods are disclosed.

Inventors

• Naveen KAUSHIK
• Michael A. Smith
• Albert Fayrushin
• Anna Maria Conti
• Haitao Liu

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20250910

Claims (20)

1. 1 . A method used in forming memory circuitry, comprising: forming a vertical fin in semiconductive material and that extends horizontally between two horizontally-spaced regions of the semiconductive material; forming a gate insulator over a top surface of each of the two horizontally-spaced regions of the semiconductive material and over a top surface and opposing lateral side surfaces of the vertical fin; forming a conductive gate over the gate insulator and over the top surface and opposing lateral side surfaces of the vertical fin, the conductive gate also being formed over the gate insulator that is over two intermediate regions of the two horizontally-spaced regions that are individually horizontally between the vertical fin and a distal region in individual of the two horizontally-spaced regions; using the conductive gate as a mask while ion implanting a conductivity-increasing dopant into the semiconductive material of the distal region that is in the individual two horizontally-spaced regions and forming therefrom a lightly-doped region of the conductivity-increasing dopant in the semiconductive material of the distal region, the two intermediate regions and vertical fin there-between comprising a channel region; forming a highest-doped region of the conductivity-increasing dopant in the distal region and that is horizontally spaced from the two intermediate regions, the lightly-doped region and the highest-doped region comprising one of two source/drain regions that are individually in one of the two horizontally-spaced regions; the source/drain regions, the channel region, the conductive gate, and the gate insulator comprising a horizontal high voltage transistor; and forming strings of NAND memory cells, the horizontal high voltage transistor being operatively electrically coupled with at least one of the strings.
2. 2 . The method of claim 1 comprising removing the gate insulator from being atop the top surface of the distal region of each of the two horizontally-spaced regions of the semiconductive material.
3. 3 . The method of claim 2 wherein the removing occurs before the ion implanting.
4. 4 . The method of claim 1 comprising forming the highest-doped region after forming the lightly-doped region.
5. 5 . The method of claim 1 comprising forming multiple of said horizontal high voltage transistor, the horizontal high voltage transistor comprising a wordline driver transistor of wordline driver circuitry, the wordline driver transistor being directly electrically coupled to a wordline of the strings of NAND memory cells.
6. 6 . The method of claim 1 comprising forming multiple of said vertical fin.
7. 7 . The method of claim 1 wherein the horizontal high voltage transistor has a horizontal current flow direction through the vertical fin, the lightly-doped region being directly against two laterally-opposing sides of the highest-doped region in a vertical cross-section that is parallel the horizontal current flow direction.
8. 8 . The method of claim 1 wherein the horizontal high voltage transistor has a horizontal current flow direction through the vertical fin and the lightly-doped region has a maximum vertical thickness, the individual of the two intermediate regions having a maximum dimension parallel the horizontal current flow direction that is at least 5% of the maximum vertical thickness of the lightly-doped region.
9. 9 . The method of claim 8 wherein the maximum dimension parallel the horizontal current flow direction is at least 8% of the maximum vertical thickness of the lightly-doped region.
10. 10 . The method of claim 9 wherein the maximum dimension parallel the horizontal current flow direction is at least 15% of the maximum vertical thickness of the lightly-doped region.
11. 11 . The method of claim 10 wherein the maximum dimension parallel the horizontal current flow direction is at least 20% of the maximum vertical thickness of the lightly-doped region.
12. 12 . The method of claim 8 wherein the maximum dimension parallel the horizontal current flow direction is no more than 50% of the maximum vertical thickness of the lightly-doped region.
13. 13 . The method of claim 12 wherein the maximum dimension parallel the horizontal current flow direction is 15% to 30% of the maximum vertical thickness of the lightly-doped region.
14. 14 . The method of claim 1 wherein the strings are formed to extend vertically.
15. 15 . Memory circuitry comprising: strings of NAND memory cells; horizontal high voltage transistors that are operatively electrically coupled with the strings, the horizontal high voltage transistors individually comprising: two horizontally-spaced regions having a vertical fin extending horizontally there-between along a horizontal current flow direction of the transistor; two source/drain regions that are individually in one of the two horizontally-spaced regions, the two source/drain regions individually comprising: conductivity-increasing dopant in semiconductive material; a highest-doped region of the conductivity-increasing dopant that is horizontally spaced from the vertical fin; and a lightly-doped region of the conductivity-increasing dopant that is beneath and laterally aside the highest-doped region between the highest-doped region and the vertical fin, the lightly-doped region being horizontally spaced from the vertical fin by an intermediate region of one of the two horizontally-spaced regions; a channel region horizontally between the two source/drain regions, the channel region being in the vertical fin and in each intermediate region that is horizontally between the lightly-doped region and the vertical fin in individual of the two horizontally-spaced regions; and a conductive gate operatively over a top surface and opposing lateral side surfaces of the vertical fin and over a top surface of each intermediate region.
16. 16 . The memory circuitry of claim 15 wherein the horizontal high voltage transistors individually comprise a wordline driver transistor of wordline driver circuitry, the wordline driver transistor being directly electrically coupled to a wordline of the strings of NAND memory cells.
17. 17 . The memory circuitry of claim 15 wherein the horizontal high voltage transistors individually comprise multiple of said vertical fin.
18. 18 . The memory circuitry of claim 15 wherein the lightly-doped region is directly against two laterally-opposing sides of the highest-doped region in a vertical cross-section that is parallel the horizontal current flow direction.
19. 19 . The memory circuitry of claim 15 wherein the lightly-doped region has a maximum vertical thickness, each intermediate region having a maximum dimension parallel the horizontal current flow direction that is at least 5% of the maximum vertical thickness of the lightly-doped region.
20. 20 . The memory circuitry of claim 19 wherein the maximum dimension parallel the horizontal current flow direction is at least 8% of the maximum vertical thickness of the lightly-doped region.

Description

TECHNICAL FIELD Embodiments disclosed herein pertain to memory circuitry and to methods used in forming memory circuitry BACKGROUND Memory is one type of integrated circuitry and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digitlines (which may also be referred to as bitlines, data lines, or sense lines) and access lines (which may also be referred to as wordlines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line. Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information. A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Flash memory is one type of memory and has numerous uses in modern computers and devices. For instance, modern personal computers may have BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid state drives to replace conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features. NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor. Memory arrays may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks), and memory planes, for example as shown and described in any of U.S. Patent Application Publication Nos. 2015/0228651, 2016/0267984, and 2017/0140833. The memory blocks may at least in part define longitudinal outlines of individual wordlines in individual wordline tiers of vertically-stacked memory cells. Connections to these wordlines may occur in a so-called “stair-step structure” at an end or edge of an array of the vertically-stacked memory cells. The stair-step structure includes individual “stairs” (alternately termed “steps” or “stair-steps”) that define contact regions of the individual wordlines upon which elevationally-extending conductive vias contact to provide electrical access to the wordlines. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-3 are diagrammatic views of a construction in process in accordance with some embodiments of the invention. FIGS. 4-21 are diagrammatic sequential views of the construction of FIGS. 1-3 in process in accordance with some embodiments of the invention. FIG. 22 is a simplified block diagram of a memory in communication with a processor as part of an electronic system, according to an embodiment. FIGS. 23A and 23B are schematics of portions of an array of memory cells as could be used in a memory of the type described with reference to FIG. 22. DETAILED D