US-20260128098-A1 - HIGH BANDWIDTH PARALLEL PROGRAM METHOD WITH DYNAMIC LATCH FOR THREE-DIMENSIONAL MEMORY ARRAY

US20260128098A1US 20260128098 A1US20260128098 A1US 20260128098A1US-20260128098-A1

Abstract

A three-dimensional memory device is provided. The device comprises an array of memory cells comprising a plurality of memory blocks having a first memory block. The first memory block includes a plurality of sets of sub-blocks. The device further comprises a global bit line; a controller; and a plurality of dynamic latch devices connected between the global bit line and the plurality of sets of sub-blocks. A first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of sub-blocks. Different dynamic latch devices of the plurality of dynamic latch devices are connected to different sets of sub-blocks. The first dynamic latch device is controllable by the controller to store program data during a program operation in which the first set of sub-blocks connected to the first dynamic latch device are unselected sub-blocks during the program operation.

Inventors

Tomoko Ogura Iwasaki
Tomoharu Tanaka
June Lee
Yoshiaki Fukuzumi

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251027

Claims (18)

1 . A three-dimensional memory device comprising: an array of memory cells comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks; a global bit line; a controller; and a plurality of dynamic latch devices connected between the global bit line and the plurality of sets of sub-blocks, wherein: a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of sub-blocks of the plurality of sets of sub-blocks, different dynamic latch devices of the plurality of dynamic latch devices are connected to different sets of sub-blocks of the plurality of sets of sub-blocks, and the first dynamic latch device is controllable by the controller to store program data during a program operation in which the first set of sub-blocks connected to the first dynamic latch device are unselected sub-blocks during the program operation.
2 . The three-dimensional memory device of claim 1 , further comprising a page buffer, wherein during the program operation, the controller is configured to: obtain the program data from the first dynamic latch device instead of from the page buffer; and perform the program operation of one or more sub-blocks that are not connected to the first dynamic latch device, the one or more sub-blocks are selected sub-blocks in the plurality of sets of sub-blocks for performing the program operation.
3 . The three-dimensional memory device of claim 1 , wherein each of the plurality of dynamic latch devices comprises: a storage device; a plurality of write transistors connected between the global bit line and the storage device; and a plurality of read transistors connected between the storge device and a source line; wherein: the storage device is connected between the plurality of write transistors and the plurality of read transistors, the storage device being controllable to store data at a sense memory node.
4 . The three-dimensional memory device of claim 1 , wherein the controller is further configured to: cause word lines connected to all sets of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage based on a single programming pulse, such that pillars of memory cells in the plurality sets of sub-blocks are charged up and floating; cause the global bit line to rise to a global bit line voltage; perform, for each sub-block in the plurality set of the plurality of sets sub-blocks: activate one or more write transistors in a dynamic latch device of the plurality of dynamic latch devices and activate a select gate of a sub-block in a corresponding set of sub-blocks of the plurality of sets of sub-blocks; modulate the global bit line voltage to remain the same or change based on the program data; cause word lines connected to a selected sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage; and program multiple selected sub-blocks via the plurality of dynamic latches based on a single programming pulse.
5 . The three-dimensional memory device of claim 1 , wherein the controller is configured to program in parallel, using the plurality of dynamic latch devices, at least four sub-blocks of the first memory block and at least four other sub-blocks in another memory block.
6 . The three-dimensional memory device of claim 1 , wherein a dynamic latch device of the plurality of latch devices comprises a plurality of read transistors configured to perform sense amplification during a read operation.
7 . The three-dimensional memory device of claim 1 , wherein the controller is further configured to: cause the global bit line to rise to a global bit line voltage; activate one or more write transistors in each of the plurality of dynamic latch devices and active a select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks; cause word lines connected to a selected memory cell of a sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage; cause word lines connected to unselected memory cells of the sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage; deactivate one or more write transistors in each of the plurality of dynamic latch devices and activate another select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks; and serially activate, for each of the plurality of dynamic latch devices, one or more read transistors, and cause multiple selected sub-blocks to be read using the plurality of dynamic latch device based on a single read pulse.
8 . The three-dimensional memory device of claim 1 , wherein the first set of sub-blocks comprises at least two sub-blocks, the at least two sub-blocks being connected to the first dynamic latch device and no other dynamic latch devices.
9 . The three-dimensional memory device of claim 1 , wherein the plurality of dynamic latch devices are physically disposed above the array of memory cells, wherein other latch devices in a page buffer are physically disposed below the array of memory cells.
10 . The three-dimensional memory device of claim 1 , wherein the plurality of dynamic latch devices comprises at least 20 dynamic latch devices per global bit line per plane.
11 . The three-dimensional memory device of claim 1 , further comprising a page buffer connected to the global bit line, wherein the controller is further configured to perform operations to cause at least two selected sub-blocks of the plurality of sets of sub-blocks to be programed in parallel using program data obtained from the page buffer.
12 . The three-dimensional memory device of claim 1 , wherein the controller is configured to cause the program data to be stored at a sense memory node in the first dynamic latch device.
13 . The three-dimensional memory device of claim 12 , wherein the first dynamic latch device comprises a storage device comprising a switch transistor having a gate terminal connected to the sense memory node.
14 . The three-dimensional memory device of claim 1 , wherein each of the plurality of dynamic latch devices is connected to between one and four sub-blocks.
15 . The three-dimensional memory device of claim 1 , wherein the array of memory cells comprises tri-level or quad-level memory cells.
16 . A method performed by a three-dimensional memory device comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks, the method comprising: causing a global bit line to rise to a global bit line voltage; activating one or more write transistors in each of a plurality of dynamic latch devices and activating a select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks; causing word lines connected to a selected memory cell of a sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage; causing word lines connected to unselected memory cells of the sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage; deactivating one or more write transistors in each of the plurality of dynamic latch devices and activating another select gate of one sub-block in each set of sub-blocks of the plurality of sets of sub-blocks; and serially activating, for each of the plurality of dynamic latch devices, one or more read transistors, and causing multiple selected sub-blocks to be read using the plurality of dynamic latch device based on a single read pulse.
17 . A method performed by a three-dimensional memory device comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks, the method comprising: causing word lines connected to all sets of sub-blocks of the plurality of sets of sub-blocks to rise to a first word line voltage based on a single programming pulse, such that pillars of memory cells in the plurality sets of sub-blocks are charged up and floating; causing the global bit line to rise to a global bit line voltage; performing, for each sub-block in the plurality set of the plurality of sets sub-blocks: activating one or more write transistors in a dynamic latch device of a plurality of dynamic latch devices and activating a select gate of a sub-block in a corresponding set of sub-blocks of the plurality of sets of sub-blocks; modulating the global bit line voltage to remain the same or change based on program data; causing word lines connected to a selected sub-block in each set of sub-blocks of the plurality of sets of sub-blocks to rise to a second word line voltage; and programing multiple selected sub-blocks via the plurality of dynamic latches based on a single programming pulse.
18 . A memory system comprising: a processor; and a memory device coupled to the processor, the memory device comprising: an array of memory cells comprising a plurality of memory blocks having a first memory block, the first memory block including a plurality of sets of sub-blocks; a global bit line; a controller; and a plurality of dynamic latch devices connected between the global bit line and the plurality of sets of sub-blocks, wherein: a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of sub-blocks of the plurality of sets of sub-blocks, different dynamic latch devices of the plurality of dynamic latch devices are connected to different sets of sub-blocks of the plurality of sets of sub-blocks, and the first dynamic latch device is controllable by the controller to store program data during a program operation in which the first set of sub-blocks connected to the first dynamic latch device are unselected sub-blocks during the program operation.

Description

RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/716,935 filed on November 6, 2024, titled “HIGH BANDWIDTH PARALLEL PROGRAM METHOD WITH DYNAMIC LATCH FOR THREE-DIMENSIONAL MEMORY ARRAY.” The contents of U.S. Provisional Application No. 63/716,935 are hereby incorporated by reference in their entirety for all purposes. TECHNICAL FIELD This disclosure relates to one or more systems for memory, including techniques related to dynamic latch devices used for perform parallel read and program operations of a three-dimensional non-volatile memory array in a memory device. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Information can also be erased from the memory cells and new information can be stored in the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory device in communication with a memory system controller of a memory system, in accordance with examples as disclosed herein. FIGS. 2A-2C are illustrative schematics of portions of an array of memory calls in a memory device, in accordance with examples as disclosed herein. FIG. 2D illustrates an example of a memory device including multiple blocks of memory cells in accordance with examples as disclosed herein. FIG. 3 is a block diagram of an example apparatus for implementing one or more systems and for performing one or more methods described herein, in accordance with examples as disclosed herein. FIGS. 4A and 4B illustrate an example three-dimensional structure of a memory device in accordance with examples as disclosed herein. FIG. 5 is a block diagram illustrating portions of a memory device with dynamic latch devices disposed above a three-dimensional memory array in accordance with examples as disclosed herein. FIG. 6 is an example schematic of two dynamic latch devices each connected to a set of sub-blocks in a memory block for storing program data, in accordance with example as disclosed herein. FIG. 7A is an example of two dynamic latch devices each connected to a set of sub-blocks in a memory block used for performing program operations in parallel to multiple sub-blocks, in accordance with example as disclosed herein. FIG. 7B is a flowchart showing a method of programing a single sub-block using a dynamic latch device, in accordance with examples as disclosed herein. FIG. 7C is a flowchart showing a method of programing multiple sub-blocks in parallel using the dynamic latch devices with a single programming pulse, in accordance with examples as disclosed herein. FIG. 8A is an example of two dynamic latch devices each connected to a set of sub-blocks in a memory block used for performing read or program verify operations in parallel from multiple sub-blocks, in accordance with example as disclosed herein. FIG. 8B is a flowchart showing a method of reading from a single sub-block using a dynamic latch device, in accordance with examples as disclosed herein. FIG. 8C is a flowchart showing a method of reading multiple sub-blocks in parallel using multiple dynamic latch devices, in accordance with examples as disclosed herein. FIG. 9 is an example waveform for showing applying a program pulse to cause the voltage of a floating pillar to change in accordance with examples as disclosed herein. DETAILED DESCRIPTION Aspects of the present disclosure are directed to dynamic latch devices operated with a three-dimensional (3D) non-volatile memory array in a memory device for performing memory operations