US-20260128100-A1 - SYSTEMS AND METHODS FOR VARYING MAXIMUM PROGRAM VOLTAGE

US20260128100A1US 20260128100 A1US20260128100 A1US 20260128100A1US-20260128100-A1

Abstract

A memory device is provided. The memory device includes an array of memory cells. The memory cells are multiple-level memory cells. The memory device further includes a controller configured to perform: initiating a programming operation to program selected memory cells of the array of memory cells; and determining a remaining program fail count prior to a last step of the programming operation. The last step of the programming operation corresponds to programming a last level of the selected memory cells of the array of memory cells. The controller is further configured to perform determining a last level program voltage step based on the remaining program fail count value; and causing the last level of the selected memory cells to be programmed based on the last level program voltage step.

Inventors

Jeffrey S. McNeil

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251104

Claims (18)

1 . A memory device comprising: an array of memory cells, the memory cells being multiple-level memory cells; and a controller, coupled with the array of memory cells, the controller being configured to perform: initiating a programming operation to program selected memory cells of the array of memory cells; determining a remaining program fail count prior to a last step of the programming operation, wherein the last step of the programming operation corresponds to programming a last level of the selected memory cells of the array of memory cells; determining a last level program voltage step based on the remaining program fail count value; and causing the last level of the selected memory cells to be programmed based on the last level program voltage step.
2 . The memory device of claim 1 , wherein the controller is further configured to perform, prior to determining the remaining program fail count: determining that, during the programming operation, a next programming pulse is the last programming pulse for programming the last level of the selected memory cells.
3 . The memory device of claim 2 , wherein determining that the next programming pulse is the last programming pulse is based on at least one of: a current level program voltage; or a remaining program fail count threshold.
4 . The memory device of claim 1 , wherein the remaining program fail count represents a remaining number of bits to be programed for the last level of the selected memory cells.
5 . The memory device of claim 4 , further comprising a page buffer, wherein the controller is further configured to perform: storing a representation of the remaining number of bits to be programed in the page buffer of the array of memory cells.
6 . The memory device of claim 1 , wherein the determining the last level program voltage step is based on a fail-count threshold lookup table representing relations between fail-count threshold values and corresponding program voltage steps.
7 . The memory device of claim 6 , wherein the fail-count threshold values comprise fail-count percentage thresholds associated with the corresponding program voltage steps.
8 . The memory device of claim 7 , wherein the fail-count percentage thresholds include at least one of the following remaining bit percentage thresholds: greater than 25%, between 25% and 15%, between 14% and 8%, between 7% and 3%, or between 2% and 1%.
9 . The memory device of claim 7 , wherein the corresponding program voltage steps include at least one of the following steps: 500 mV, 400 mV, 300 mV, 200 mV, or 100 mV.
10 . The memory device of claim 6 , wherein the relations represented by the fail-count threshold lookup table are further between the fail-count threshold values, one or more environmental factors, one or more manufacturing factors and the corresponding program voltage steps.
11 . The memory device of claim 1 , wherein during the programming operation, the controller is further configured to cause a counter to obtain, from a page buffer, the remaining program fail count representing the remaining number of bits to be programed.
12 . The memory device of claim 1 , wherein the last level program voltage step is a variable program voltage step.
13 . The memory device of claim 1 , wherein the last level program voltage step meets a threshold for omitting a program-verify phase for the last step of the programming operation.
14 . The memory device of claim 1 , wherein based on the remaining program fail count threshold, the last level program voltage step is reduced relative to a predetermined last level voltage step.
15 . The memory device of claim 1 , wherein the last level program voltage step is configured to be no greater than a maximum program voltage step threshold during the programming operation.
16 . The memory device of claim 1 , wherein during the programming operation, program voltages other than the last level program voltage are fixed.
17 . A memory system comprising: a processor; and a memory device coupled to the processor, the memory device comprising: an array of memory cells, the memory cells being multiple-level memory cells; and a controller, coupled with the array of memory cells, the controller being configured to perform: initiating a programming operation to program selected memory cells of the array of memory cells; determining a remaining program fail count prior to a last step of the programming operation, wherein the last step of the programming operation corresponds to programming a last level of the selected memory cells of the array of memory cells; determining a last level program voltage step based on the remaining program fail count value; and causing the last level of the selected memory cells to be programmed based on the last level program voltage step.
18 . A method for programming multi-level memory cells in an array of memory cells in a memory device, the method comprising: initiating a programming operation for a word line connected to selected memory cells of the array of memory cells; determining a remaining program fail count prior to a last step of the programming operation, wherein the last step of the programming operation corresponds to programming a last level of the selected memory cells of the array of memory cells; determining a last level program voltage step based on the remaining program fail count; and causing the last level of the selected memory cells to be programmed based on the last level program voltage step.

Description

RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/716,877, filed on Nov. 6, 2024, entitled “SYSTEMS AND METHODS FOR VARYING MAXIMUM PROGRAM VOLTAGE.” The contents of U.S. Provisional Application No. 63/716,877 are incorporated by reference herein in their entirety for all purposes. TECHNICAL FIELD This disclosure relates to one or more systems for memory, including techniques for varying maximum program voltage during programming operations of a memory device. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, retrieve, determine) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign) states to the memory cells. Information can also be erased from the memory cells and new information can be stored in the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory device in communication with a memory system controller of a memory system, in accordance with examples as disclosed herein. FIGS. 2A-2C are illustrative schematics of portions of an array of memory calls in a memory device, in accordance with examples as disclosed herein. FIG. 3 is a block diagram of an example apparatus for implementing one or more systems and for performing one or more methods described herein, in accordance with examples as disclosed herein. FIG. 4 illustrates an example cell threshold voltage distribution diagram for an TLC memory device and example programming pulses. FIG. 5 illustrates an example cell threshold voltage distribution diagram for a TLC memory device with variable last level program step and example programming pulses in accordance with examples as disclosed herein. FIG. 6 is an example look-up table for determining the last level program step, in accordance with examples as disclosure herein. FIG. 7 illustrates a flowchart showing a method or methods that support techniques for varying the last level program step for programming a multi-level memory device in accordance with examples as disclosed herein. DETAILED DESCRIPTION A memory device may include many memory cells. For an single level cell (SLC), each memory cell is configured to store one bit of information. Nowadays, a memory device may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, as tri-level cells (TLCs) if configured to each store three bits of information, as quad-level cells (QLCs) if configured to each store four bits of information, or more generically as multiple-level memory cells. Multiple-level memory cells may provide greater density of storage relative to SLC memory cells. Multiple-level memory cells have multiple threshold voltage levels for storing multiple bits of data. For example, an MLC cell has four threshold voltage levels for storing two bits of data. The two bits per cell belong to two different pages called the lower page (LP) and upper page (UP). A TLC cell has eight threshold voltage levels for storing three bits of data. The three bits per cell belong to three different pages called the lower page (LP), the upper page (UP), and the extra page (XP). Data are stored into multiple-level memory cells by programming them into different pages. An incremental step pulse programming (ISPP) technique is often used for programming multiple-level memory cells. For example, for programming MLC or TLC memory cells, multiple programming pulses are applied to the word line connected to the memory cells. Each of the multiple programming pulses is increased by a voltage st