US-20260128101-A1 - PROGRAMMING METHOD FOR NON-VOLATILE MEMORY CELLS

US20260128101A1US 20260128101 A1US20260128101 A1US 20260128101A1US-20260128101-A1

Abstract

A method of programming a memory cell to a target program state associated with a target read current, comprising applying a first pulse of programming voltages that includes a first control gate voltage, applying a second pulse of programming voltages that includes a second control gate voltage, performing a read operation that includes detecting currents through the memory cell for different voltages applied to the control gate, determining a first read voltage for the control gate using the detected currents that corresponds to the target read current, determining a target programming voltage using the second voltage, the first read voltage, a control gate nominal read voltage and a tuning factor, erasing the memory cell, applying a third pulse of programming voltages that includes the first control gate voltage, and applying a fourth pulse of programming voltages that includes the target programming voltage applied to the control gate.

Inventors

Viktor Markov
Alexander Kotov

Assignees

SILICON STORAGE TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20250117

Claims (20)

1 . A method of programming a memory cell to a target program state that is associated with a control gate nominal read voltage and a target read current, the memory cell comprising: a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region, a floating gate disposed over and insulated from a first portion of the channel region, for controlling a conductivity of the first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, for controlling a conductivity of a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the source region, and disposed adjacent to and insulated from the floating gate; the method comprising: applying a first pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the first pulse of programming voltages includes a first voltage applied to the control gate, applying a second pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the second pulse of programming voltages includes a second voltage applied to the control gate, performing a read operation that includes detecting currents through the channel region for different voltages applied to the control gate, determining a first read voltage for the control gate using the detected currents that corresponds to the target read current, determining a target programming voltage using the second voltage, the first read voltage, the control gate nominal read voltage and a tuning factor, erasing the memory cell, applying a third pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the third pulse of programming voltages includes the first voltage applied to the control gate, and applying a fourth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fourth pulse of programming voltages includes the target programming voltage applied to the control gate.
2 . The method of claim 1 , wherein the second voltage is greater than the first voltage.
3 . The method of claim 1 , wherein the determination of the target programming voltage is performed according to: the second voltage+(the control gate nominal read voltage−the first read voltage)*the tuning factor.
4 . The method of claim 1 , further comprising: erasing the memory cell before the application of the first pulse of programming voltages.
5 . The method of claim 1 , further comprising: erasing the memory cell after the application of the fourth pulse of programming voltages, and then: applying a fifth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fifth pulse of programming voltages includes the first voltage applied to the control gate, and applying a sixth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the sixth pulse of programming voltages includes the target programming voltage applied to the control gate.
6 . A method of programming memory cells to a target program state that is associated with a control gate nominal read voltage and a target read current, where each of the memory cells comprises: a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region, a floating gate disposed over and insulated from a first portion of the channel region, for controlling a conductivity of the first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, for controlling a conductivity of a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the source region, and disposed adjacent to and insulated from the floating gate; the method comprising, for each of the memory cells: applying a first pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the first pulse of programming voltages includes a first voltage applied to the control gate, applying a second pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the second pulse of programming voltages includes a second voltage applied to the control gate, performing a read operation that includes detecting currents through the channel region for different voltages applied to the control gate, determining a first read voltage for the control gate using the detected currents that corresponds to the target read current, determining a target programming voltage using the second voltage, the first read voltage, the control gate nominal read voltage and a tuning factor, erasing the memory cell, applying a third pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the third pulse of programming voltages includes the first voltage applied to the control gate, and applying a fourth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fourth pulse of programming voltages includes the target programming voltage applied to the control gate.
7 . The method of claim 6 , wherein the second voltage is greater than the first voltage.
8 . The method of claim 6 , comprising: identifying a first plurality of the memory cells for which a first value of the target programming voltage is determined, and identifying a second plurality of the memory cells for which a second value of the target programming voltage is determined, wherein the first value is different than the second value, wherein the application of the third and fourth pulses of programming voltages for the first plurality of the memory cells is performed before the application of the third and fourth pulses of programming voltages for the second plurality of the memory cells.
9 . The method of claim 6 , wherein for each of the memory cells, the determination of the target programming voltage is performed according to: the second voltage+(the control gate nominal read voltage−the first read voltage)*the tuning factor.
10 . The method of claim 6 , wherein for each of the memory cells, further comprising: erasing the memory cell before the application of the first pulse of programming voltages.
11 . The method of claim 6 , wherein for each of the memory cells, further comprising: erasing the memory cell after the application of the fourth pulse of programming voltages, and then: applying a fifth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fifth pulse of programming voltages includes the first voltage applied to the control gate, and applying a sixth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the sixth pulse of programming voltages includes the target programming voltage applied to the control gate.
12 . A semiconductor device, comprising: a memory cell comprising: a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region, a floating gate disposed over and insulated from a first portion of the channel region, for controlling a conductivity of the first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, for controlling a conductivity of a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the source region, and disposed adjacent to and insulated from the floating gate; and control circuitry to program the memory cell to a target program state that is associated with a control gate nominal read voltage and a target read current, by: apply a first pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the first pulse of programming voltages includes a first voltage applied to the control gate, apply a second pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the second pulse of programming voltages includes a second voltage applied to the control gate, perform a read operation that includes detection of currents through the channel region for different voltages applied to the control gate, determine a first read voltage for the control gate using the detected currents that corresponds to the target read current, determine a target programming voltage using the second voltage, the first read voltage, the control gate nominal read voltage and a tuning factor, erase the memory cell, apply a third pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the third pulse of programming voltages includes the first voltage applied to the control gate, and apply a fourth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fourth pulse of programming voltages includes the target programming voltage applied to the control gate.
13 . The semiconductor device of claim 12 , wherein the second voltage is greater than the first voltage.
14 . The semiconductor device of claim 12 , wherein the determination of the target programming voltage is according to: the second voltage+(the control gate nominal read voltage−the first read voltage)*the tuning factor.
15 . The semiconductor device of claim 12 , wherein the control circuitry to: erase the memory cell before the application of the first pulse of programming voltages.
16 . The semiconductor device of claim 12 , wherein the control circuitry to: erase the memory cell after the application of the fourth pulse of programming voltages, and then: apply a fifth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fifth pulse of programming voltages includes the first voltage applied to the control gate, and apply a sixth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the sixth pulse of programming voltages includes the target programming voltage applied to the control gate.
17 . A semiconductor device, comprising: a plurality of memory cells, wherein each of the memory cells comprises: a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region, a floating gate disposed over and insulated from a first portion of the channel region, for controlling a conductivity of the first portion of the channel region, a select gate disposed over and insulated from a second portion of the channel region, for controlling a conductivity of a second portion of the channel region, a control gate disposed over and insulated from the floating gate, and an erase gate disposed over and insulated from the source region, and disposed adjacent to and insulated from the floating gate; and control circuitry to program the memory cells to a target program state that is associated with a control gate nominal read voltage and a target read current, by, for each of the memory cells: apply a first pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the first pulse of programming voltages includes a first voltage applied to the control gate, apply a second pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the second pulse of programming voltages includes a second voltage applied to the control gate, perform a read operation that includes detection of currents through the channel region for different voltages applied to the control gate, determine a first read voltage for the control gate using the detected currents that corresponds to the target read current, determine a target programming voltage using the second voltage, the first read voltage, the control gate nominal read voltage and a tuning factor, erase the memory cell, apply a third pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the third pulse of programming voltages includes the first voltage applied to the control gate, and apply a fourth pulse of programming voltages to the source region, the select gate, the erase gate and the control gate, wherein the fourth pulse of programming voltages includes the target programming voltage applied to the control gate.
18 . The semiconductor device of claim 17 , wherein the second voltage is greater than the first voltage.
19 . The semiconductor device of claim 17 , wherein the control circuitry to: identify a first plurality of the memory cells for which a first value of the target programming voltage is determined, and identify a second plurality of the memory cells for which a second value of the target programming voltage is determined, wherein the first value is different than the second value, wherein the application of the third and fourth pulses of programming voltages for the first plurality of the memory cells is performed before the application of the third and fourth pulses of programming voltages for the second plurality of the memory cells.
20 . The semiconductor device of claim 17 , wherein for each of the memory cells, the determination of the target programming voltage is according to: the second voltage+(the control gate nominal read voltage−the first read voltage)*the tuning factor.

Description

RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/717,847, filed Nov. 7, 2024, and which is incorporated herein by reference. FIELD OF THE INVENTION The present disclosure relates to non-volatile memory cells of semiconductor devices, and more particularly to a technique of programming memory cells. BACKGROUND OF THE INVENTION Split-gate non-volatile memory semiconductor devices are well known in the art. See for example U.S. Pat. No. 7,868,375, which discloses a four-gate memory cell configuration, and which is incorporated herein by reference for all purposes. Specifically, FIG. 1 of the present disclosure illustrates a pair of split gate non-volatile memory cells 10 each with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12. The source region 14 can be referred to as a source line SL (because it commonly is connected to other source regions for other non-volatile memory cells 10 in the same row or column), and the drain region 16 is commonly connected to a bit line. A channel region 18 of the substrate 12 extends between the source/drain regions 14/16. A floating gate 20 is disposed over (i.e., vertically over and laterally overlapping) and insulated from (and directly controls the conductivity of) a first portion of the channel region 18 (and partially over, and insulated from, the source region 14). A control gate 22 is disposed over, and insulated from, the floating gate 20. A select gate 24 (also referred to as a word line gate) is disposed over, and insulated from, and directly controls the conductivity of, a second portion of the channel region 18. An erase gate 26 is disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. The erase gate 26 can include a notch that faces an edge of the floating gate 20. A plurality of such memory cells 10 can be arranged in rows and columns to form a memory cell array, as illustrated in FIG. 2. While FIG. 1 only shows a pair of memory cells 10 (sharing a common source region 14 and erase gate 26), the memory cell pairs can be placed end to end to form a column of memory cells 10 (where the memory cell pairs can share a common drain region 16). While only two such columns are shown in FIG. 2, there can be many such columns. Each column can include a bit line 16a electrically connecting together all the drain regions 16 in the column. Each row of memory cells 10 can include a control gate line 22a electrically connecting together all the control gates 22 in the row of memory cells 10. For example, all the control gates 22 in each row of memory cells 10 can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell 10 serves as its control gate 22. Each row of memory cells 10 can include a select gate line 24a electrically connecting together all the select gates 24 in the row of memory cells 10. For example, all the select gates 24 in each row of memory cells 10 can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell 10 serves as its select gate 24. Each row of memory cell pairs can include an erase gate line 26a electrically connecting together all the erase gates 26 in the row of memory cell pairs. For example, all the erase gates 26 in each row of memory cell pairs can be formed as a continuous line of conductive material, where a portion of the continuous line passing through any given memory cell pair serves as its erase gate 26. Finally, each row of memory cell pairs can include a source line 14a electrically connecting together all the source regions 14 in the row of memory cell pairs. For example, all the source regions 14 in each row of memory cell pairs can be formed as a continuous line of conductive diffusion in the substrate 12, where a portion of the continuous line passing through any given memory cell pair serves as its source region 14. Various combinations of voltages are applied to the control gate 22, select gate 24, erase gate 26 and source and drain regions 14/16, to program the split gate non-volatile memory cell 10 (i.e., inject electrons onto the floating gate 20), to erase the split gate non-volatile memory cell 10 (i.e., remove electrons from the floating gate 20), and to read the split gate non-volatile memory cell 10 (i.e., measure or detect the conductivity of the channel region 18, by for example measuring or detecting an electrical current (also referred to as a read current or current) through the channel region 18, to determine the program state of the floating gate 20). Split gate non-volatile memory cell 10 can be operated in a digital manner, where the split gate non-volatile memory cell 10 is set to one of only two possible states: a programmed state and an erased state. The split gate non-volatile memory cell 10 is erased by placing a high posi