US-20260128102-A1 - NAND MEMORY WITH WORD LINE AND SWITCH TRANSISTOR VOLTAGES

Abstract

Disclosed herein are related to a memory device and a method of operating the memory device. In one aspect, a voltage supply circuit is configured to apply, during a first time period, a first voltage to a gate of a first switch transistor connected to a first block of memory cells through a first word line to enable the first switch transistor. In one aspect, the voltage supply circuit is configured to apply, during the first time period, a second voltage lower than the first voltage to the first word line through the first switch transistor. In one aspect, the voltage supply circuit is configured to apply, during the first time period, a third voltage lower than the second voltage to a gate of a second switch transistor connected to a second block of memory cells through a second word line to disable the second switch transistor.

Inventors

• Hidehiro Shiga

Assignees

• KIOXIA CORPORATION

Dates

Publication Date

20260507

Application Date

20251219

Priority Date

20220704

Claims (17)

1. 1 . A device comprising: a first block of memory cells; a second block of memory cells; a first word line connected to gates of the first block of memory cells; a second word line connected to gates of the second block of memory cells; a first switch transistor connected to the first word line; a second switch transistor connected to the second word line; a voltage supply circuit connected to the first switch transistor and the second switch transistor, the voltage supply circuit configured to: apply, during a first time period, a first voltage to a gate of the first switch transistor to enable the first switch transistor, apply, during the first time period, a second voltage lower than the first voltage to the first word line through the first switch transistor, and apply, during the first time period, a third voltage lower than the second voltage to a gate of the second switch transistor to disable the second switch transistor; and a first line connected to the voltage supply circuit, wherein the first switch transistor is connected between the first line and the first word line, wherein the second switch transistor is connected between the first line and the second word line, wherein the voltage supply circuit is configured to apply, during the first time period, the second voltage to the first word line through the first line and the first switch transistor, and apply, during a second time period before the first time period, a fourth voltage to i) the gate of the first switch transistor, ii) the gate of the second switch transistor, and iii) the first line, and wherein the fourth voltage is between the first voltage and the third voltage.
2. 2 . The device of claim 1 , wherein the voltage supply circuit is configured to apply, during the first time period, i) the first voltage to the gate of the first switch transistor, and ii) the second voltage to the first word line, to erase data stored by the first block of memory cells.
3. 3 . The device of claim 2 , wherein data stored by the second block of memory cells is not erased during the first time period.
4. 4 . The device of claim 1 , wherein the third voltage is a negative voltage lower than a ground voltage.
5. 5 . The device of claim 4 , wherein the second voltage is the ground voltage.
6. 6 . The device of claim 4 , wherein the second voltage is another negative voltage lower than the ground voltage.
7. 7 . The device of claim 1 , wherein, during the first time period, the second word line is electrically floated to have a fourth voltage higher than the second voltage.
8. 8 . The device of claim 1 , wherein the voltage supply circuit is configured to: apply, during a second time period before the first time period, the second voltage to i) the gate of the first switch transistor, and ii) the gate of the second switch transistor.
9. 9 . The device of claim 1 , wherein a portion of the first block of memory cells is connected between a bit line and a source line, wherein a portion of the second block of memory cells is connected between the bit line and the source line, and wherein the bit line and the source line are applied with a fifth voltage higher than the second voltage during the first time period.
10. 10 . The device of claim 1 , wherein the voltage supply circuit is configured to: apply, during a third time period after the first time period, a sixth voltage higher than the first voltage to the gate of the first switch transistor to enable the first switch transistor, apply, during the third time period, the second voltage to the first word line through the first switch transistor, and apply, during the third time period, the third voltage to the gate of the second switch transistor to disable the second switch transistor.
11. 11 . A memory device comprising: a first plurality of memory cells; a second plurality of memory cells; a first word line connected to gates of the first plurality of memory cells; a second word line connected to gates of the second plurality of memory cells; a first switch transistor connected to the first word line; a second switch transistor connected to the second word line; a voltage supply circuit connected to the first switch transistor and the second switch transistor; and a first line connected to the voltage supply circuit, wherein, to erase data stored by the first plurality of memory cells, the voltage supply circuit is configured to: apply, during a first time period, a first voltage to a gate of the first switch transistor to enable the first switch transistor, apply, during the first time period, a second voltage lower than the first voltage to the first word line through the first switch transistor, and apply, during the first time period, a third voltage lower than the second voltage to a gate of the second switch transistor to disable the second switch transistor, wherein the first switch transistor is connected between the first line and the first word line, wherein the second switch transistor is connected between the first line and the second word line, wherein the voltage supply circuit is configured to apply, during the first time period, the second voltage to the first word line through the first line and the first switch transistor, and apply, during a second time period before the first time period, a fourth voltage to i) the gate of the first switch transistor, ii) the gate of the second switch transistor, and iii) the first line, and wherein the fourth voltage is between the first voltage and the third voltage.
12. 12 . The memory device of claim 11 , wherein the third voltage is a negative voltage lower than a ground voltage.
13. 13 . The memory device of claim 12 , wherein the second voltage is the ground voltage.
14. 14 . The memory device of claim 12 , wherein the second voltage is another negative voltage lower than the ground voltage.
15. 15 . The memory device of claim 11 , wherein, during the first time period, the second word line is electrically floated to have a fourth voltage higher than the second voltage.
16. 16 . A method comprising: applying, by a voltage supply circuit during a first time period, a first voltage to a gate of a first switch transistor to enable the first switch transistor, the first switch transistor connected to a first block of memory cells; applying, by the voltage supply circuit during the first time period, a second voltage lower than the first voltage to a first word line through the first switch transistor, the first word line connected to gates of the first block of memory cells; applying, by the voltage supply circuit during the first time period, a third voltage lower than the second voltage to a gate of a second switch transistor to disable the second switch transistor, the second switch transistor connected to a second block of memory cells; and connecting a first line to the voltage supply circuit, wherein, during the first time period, i) the first voltage is applied to the gate of the first switch transistor, and ii) the second voltage is applied to the first word line, to erase data stored by the first block of memory cells, wherein the first switch transistor is connected between the first line and the first word line, and wherein the second switch transistor is connected between the first line and a second word line, wherein the voltage supply circuit is configured to apply, during the first time period, the second voltage to the first word line through the first line and the first switch transistor, and apply, during a second time period before the first time period, a fourth voltage to i) the gate of the first switch transistor, ii) the gate of the second switch transistor, and iii) the first line, and wherein the fourth voltage is between the first voltage and the third voltage.
17. 17 . The method of claim 16 , wherein the second word line is coupled to gates of the second block of memory cells and is electrically floated to have a fourth voltage higher than the second voltage, and wherein data stored by the second block of memory cells is not erased during the first time period.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of and claims benefit under 35 U.S.C. § 120 to U.S. Application No. 18/181,140, filed March 9, 2023, which is based upon and claims the benefit of priority under 35 U.S.C. § 119 from Japanese Patent Application No. 2022-107934 filed on July 4, 2022, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor storage device. BACKGROUND A NAND flash memory is known as a semiconductor storage device. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration example of a memory system, according to some embodiments; FIG. 2 is a block diagram showing a configuration example of a nonvolatile memory, according to some embodiments; FIG. 3 is a diagram showing a configuration example of an array of memory blocks having a three-dimensional structure, according to some embodiments; FIG. 4 is an example of a cross-sectional view of some regions of a semiconductor storage device, according to some embodiments; FIG. 5 is a block diagram showing an example of a configuration of a voltage supply circuit and a row decoder, according to some embodiments; FIG. 6 is a layout diagram showing an example of a layout of a switch circuit group, according to some embodiments; FIG. 7 is a block diagram showing an example of a configuration of a block decoder, according to some embodiments; FIG. 8 is a circuit diagram showing an example of a configuration of a negative voltage generation circuit, according to some embodiments; FIG. 9 is a cross-sectional view illustrating a structure of an NMOS transistor in the negative voltage generation circuit, according to some embodiments; FIG. 10 is a block diagram showing an example of a configuration of a level conversion circuit, according to some embodiments; FIG. 11 is a waveform diagram showing an example of voltages for an erase operation according to one example; FIG. 12 is a waveform diagram showing an example of voltages for an erase operation, according to some embodiments; FIG. 13 is a waveform diagram showing an example of voltages for an erase operation, according to some embodiments; and FIG. 14 is a flow chart showing an example process of performing an erase operation, according to some embodiments. DETAILED DESCRIPTION Disclosed herein are related to a semiconductor storage device. In some embodiment, a semiconductor storage device includes a first block including a plurality of first memory cells, a second block including a plurality of second memory cells, a first word line connected in common to gates of the first memory cells, a second word line connected in common to gates of the second memory cells, a bit line electrically connected to one ends of the first memory cells and one ends of the second memory cells, a first signal line electrically connectable to the first word line and the second word line, a first transistor connected between the first signal line and the first word line, a second transistor connected between the first signal line and the second word line, and a voltage generation circuit configured to generate a voltage to be supplied to the first signal line, a voltage to be supplied to a gate of the first transistor, and a voltage to be supplied to a gate of the second transistor. In some embodiments, the voltage generation circuit supplies a negative voltage to the gate of the second transistor to perform an erase operation for the first memory cells. Disclosed herein are related to a device for storing data. In some embodiments, the device includes a first block of memory cells and a second block of memory cells. In some embodiments, the device includes a first word line connected to gates of the first block of memory cells, and a second word line connected to gates of the second block of memory cells. In some embodiments, the device includes a first switch transistor connected to the first word line, and a second switch transistor connected to the second word line. In some embodiments, the device includes a voltage supply circuit connected to the first switch transistor and the second switch transistor. In some embodiments, the voltage supply circuit is configured to apply, during a first time period, a first voltage to a gate of the first switch transistor to enable the first switch transistor. In some embodiments, the voltage supply circuit is configured to apply, during the first time period, a second voltage lower than the first voltage to the first word line through the first switch transistor. In some embodiments, the voltage supply circuit is configured to apply, during the first time period, a third voltage lower than the second voltage to a gate of the second switch transistor to disable the second switch transistor. During the first time period, the second word line may be electrically floated to have a fourth voltage higher than the second voltage. In some embodiment