US-20260128103-A1 - MEMORY DEVICE AND METHOD OF PROVIDING AN ADDRESS PAGE OF A REGISTER ACCESSIBLE TO EACH CLIENT

US20260128103A1US 20260128103 A1US20260128103 A1US 20260128103A1US-20260128103-A1

Abstract

A memory device may include a memory cell array, a register group and a logic controller. The register group may include a plurality of registers configured to store set values used for various operations on the memory cell array, and a specific register including a first address information of at least one accessible register selected from the plurality of registers. The logic controller may compare second address information and the first address information, and allow or block access of the accessible register based on the comparison result. The second address is received with a register access command from an external device.

Inventors

Jin Yong Seong

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260507
Application Date: 20250418
Priority Date: 20241107

Claims (18)

1 . A memory device comprising: a memory cell array; a register group including a plurality of registers configured to store set values used for operations of the memory cell array, the plurality of registers comprising a specific register including first address information of at least one accessible register selected from the plurality of registers; and a logic controller configured to compare second address information to the first address information, and to allow or block access of the accessible register based on the comparison result, wherein the second address information is input with a register access command from an external device.
2 . The memory device of claim 1 , wherein the register access command is a read command, and wherein the logic controller is further configured to read out the set value stored in the accessible register and output the set value to the external device when the first address information matches the second address information.
3 . The memory device of claim 1 , wherein the register access command is a write command, and wherein the logic controller is further configured to change the set value stored in the accessible register to a new set value input from an external device, when the first address information matches the second address information.
4 . The memory device of claim 3 , wherein the logic controller is further configured to lock access of the accessible register using a password received from the external device, after changing the set value stored in the accessible register to the new set value.
5 . The memory device of claim 1 , wherein the logic controller comprises: a locking controller configured to output a first signal for allowing or blocking access of the accessible register using a password authentication process; and an access signal generator configured to compare the first address information with the second address information, and to output a second signal for allowing or blocking access of the accessible register based on the comparison result.
6 . The memory device of claim 5 , further comprising: a register control circuit configured to control operations of the accessible registers based on the first and second signals provided from the locking controller and the access signal generator.
7 . The memory device of claim 6 , wherein the register control circuit is configured to control the register group to perform a read operation or a write operation of the accessible registers, when the first and second signals are provided from the locking controller and the access signal generator, and wherein the first and second signals indicate whether access of the accessible register is permitted.
8 . The memory device of claim 6 , wherein the register control circuit is further configured to control the register group to transmit the first address information of the specific register to the access signal generator.
9 . The memory device of claim 1 , wherein the plurality of registers comprises a plurality of first registers, and a plurality of second registers, wherein the set values of the first registers are changeable, and the set values of the second registers are not changeable, and wherein the accessible register is included in the first registers.
10 . The memory device of claim 1 , wherein the first address information comprises an initiating address and an ending address of an address range corresponding to the accessible register.
11 . A method of operating a memory device, the method comprising: reading set values used for operations of the memory device from a memory cell array and storing the set values in a plurality of registers; storing first address information of at least one accessible register of the plurality of registers in a specific register; comparing the first address information with second address information when a register access command and the second address information are received from an external device; and allowing or blocking access of the accessible register based on the comparison result.
12 . The method of claim 11 , wherein the register access command is a read command, and wherein the logic controller reads out the set value stored in the accessible register and outputs the set value to the external device when the first address information is matched with the second address information.
13 . The method of claim 11 , wherein the register access command is a write command, and wherein the logic controller changes the set value stored in the accessible register to a new set value input from an external device when the first address information is matched with the second address information.
14 . The method of claim 13 , further comprising: locking the first address information by registering a password provided from the external device, after changing the set value stored in the accessible register to the new set value.
15 . The method of claim 14 , further comprising, after locking the first address information: comparing a password provided from the external device with the registered password; and allowing or blocking the access of the accessible register based on the comparison result.
16 . The method of claim 15 , wherein at least one of a read operation and a write operation of the accessible registers is performed when a password provided from the external device is matched with the registered password, and the first address information is matched with the second address information.
17 . A memory device comprising: a register group including a plurality of registers configured to store set values used for operations of the memory device, and a specific register including first address information of at least one accessible register of the plurality of registers; and a logic controller configured to compare the first address information with second address information, and to allow access of the accessible register, when the first address information matches the second address information, wherein the second address information is input with a register access command provided from an external device.
18 . The memory device of claim 17 , wherein the logic controller is configured to compare a first password with a second password, and to allow the access of the accessible register when the first password is matched with the second password, wherein the first password is provided from the external device, and the second password is a registered password.

Description

CROSS-REFERENCES TO RELATED APPLICATION The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2024-0157206, filed on Nov. 7, 2024, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety. BACKGROUND 1. Technical Field Example embodiments relate to a memory device, and more particularly, relate to a memory device and method of providing an address range of a register accessible to each client. 2. Related Art A memory cell array of a memory device may store information for operating the memory device such as a set value in addition to user input information. The set value may include a condition or other information which sets the operation of the memory device. For example, the set condition for the operation of the memory device may include a power supply voltage and power-up time information used for a program operation, a read operation and an erase operation. The other information may include bad information (e.g., bad column address information, bad block address information, etc.), number of program/erase performances (P/E Cycle), etc. The set information may be stored as non-volatile data in the memory cell array of the memory device. When the memory device may be powered on, the data may be read out of the memory cell array and stored in a register. For example, one register may include a single set of information. Accordingly, there may be more than one register for controlling various operations of the memory device. Among a plurality of registers in a memory device, there are a very small number of registers that are commonly accessible to all clients, and whose settings may be changed. However, to prevent problems such as malfunctions and failures, access to most registers is not allowed. SUMMARY Example embodiments provide a memory device and method of providing an address range of a register accessible to each client. According to example embodiments, there may be provided a memory device. The memory device may include a memory cell array, a register group and a logic controller. The register group may include a plurality of registers configured to store set values used for operations of the memory cell array, the plurality of registers comprising a specific register including first address information of at least one accessible register selected from the plurality of registers. The logic controller may compare second address information to the first address information, and to allow or block access of the accessible register based on the comparison result. The second address information is input with a register access command from an external device. According to example embodiments, there may be provided a method of operating a memory device. Set values used for operations of the memory device may be read from a memory cell array. The set values are stored in a plurality of registers. First address information of at least one accessible register of the plurality of registers is stored in a specific register. The first address information compares with second address information when a register access command and the second address information are received from an external device. Access of the accessible register is allowed or blocked based on the comparison result. According to example embodiments, there may be provided a memory device. The memory device may a plurality of registers configured to store set values used for operations of the memory device, and a specific register including first address information of at least one accessible register of the plurality of registers. The logic controller may be configured to compare the first address information with second address information, and to allow access of the accessible register, when the first address information matches the second address information. The second address information is input with a register access command provided from an external device According to example embodiments, the logic controller is configured to compare a first password with a second password, and to allow the access of the accessible register when the first password is matched with the second password. The first password is a password provided from the external device, and the second password is a registered password. BRIEF DESCRIPTION OF THE DRAWINGS The above and another aspects, features and advantages of the subject matter of the present disclosure will be more easily understood from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. 1 illustrates an exemplary embodiment of a memory device ; FIG. 2 illustrates a logic controller of the embodiment of FIG. 1; FIG. 3 illustrates locking operations of a locking controller of the embodiment of FIG. 2; FIG. 4 illustrates accessible register address information of the embodiment of FIG. 2; FIG. 5 is a flow chart illustrating a method of operating a memory devic