US-20260128104-A1 - MEMORY DEVICE AND MEMORY SYSTEM

US20260128104A1US 20260128104 A1US20260128104 A1US 20260128104A1US-20260128104-A1

Abstract

A memory device includes a memory string. The memory string includes a first and a second string portions. The first string portion stores stored filter bits, and compares input filter bits with the stored filter bits. The second string portion stores stored computing bits, and compares input computing bits with the stored computing bits. When the input filter bits is different from the stored filter bits, the string current signal has a first current level, when the input filter bits is equal to the stored filter bits, and the input computing bits has a first difference with the stored computing bits, the string current signal has a second current level, and when the input filter bits is equal to the stored filter bits, and the input computing bits has a second difference with the stored computing bits, the string current signal has a third current level.

Inventors

PO-HAO TSENG

Assignees

MACRONIX INTERNATIONAL CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250312

Claims (20)

1 . A memory device, comprising a memory string configured to generate a string current signal, the memory string comprising: a first string portion configured to store at least one stored filter bit, and compare at least one input filter bit with the at least one stored filter bit; and a second string portion coupled in series with the first string portion, and configured to store a plurality of stored computing bits, and compare a plurality of input computing bits with the plurality of stored computing bits, wherein when an input value of the at least one input filter bit is different from a stored value of the at least one stored filter bit, the string current signal has a first current level, when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and an input value of the plurality of input computing bits has a first difference with a stored value of the plurality of stored computing bits, the string current signal has a second current level, and when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a second difference with the stored value of the plurality of stored computing bits, the string current signal has a third current level.
2 . The memory device of claim 1 , wherein each of the second current level and the third current level is larger than the first current level, and the second current level and the third current level are different from each other.
3 . The memory device of claim 2 , wherein the first difference is smaller than the second difference, and the second current level is larger than the third current level.
4 . The memory device of claim 2 , wherein when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a third difference with the stored value of the plurality of stored computing bits, the string current signal has a fourth current level, the third difference is larger than each of the first difference and the second difference, and the fourth current level is smaller than each of the second current level and the third current level.
5 . The memory device of claim 4 , wherein when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a fourth difference with the stored value of the plurality of stored computing bits, the string current signal has a fifth current level, the fourth difference is larger than the first difference and the second difference, and the fifth current level is smaller than the fourth current level, and is larger than the first current level.
6 . The memory device of claim 1 , wherein when the first string portion comprising a plurality of switch elements, when the store value of the at least one stored filter bit has a range, each of the plurality of switch elements has a first threshold voltage level.
7 . The memory device of claim 6 , wherein when the store value of the at least one stored filter bit has the range and the at least one input filter bit has a first input value, each of the plurality of switch elements is turned on, and when the store value of the at least one stored filter bit has the range and the at least one input filter bit has a second input value different from the first input value, each of the plurality of switch elements is turned on.
8 . The memory device of claim 6 , wherein the plurality of switch elements are configured to receive a plurality of word line signals, respectively, when the input value of the at least one input filter bit has the range, each of the plurality of word line signals has a first voltage level, and each of the plurality of switch elements is turned on.
9 . A memory device, comprising a memory string configured to generate a string current signal, the memory string comprising: a first string portion comprising a plurality of first switch elements, and configured to store at least one stored filter bit; and a second string portion comprising a plurality of second switch elements coupled in series with the plurality of first switch elements, and configured to store a plurality of stored computing bits, wherein the plurality of first switch elements are configured to respectively receive a plurality of first word line signals carrying at least one input filter bit, the plurality of second switch elements are configured to respectively receive a plurality of second word line signals carrying a plurality of input computing bits, when an input value of the at least one input filter bit is different from a stored value of the at least one stored filter bit, at least one of the plurality of first switch elements is turned off, when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and an input value of the plurality of input computing bits has a first difference with a stored value of the plurality of stored computing bits, the string current signal has a first current level, and when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a second difference with the stored value of the plurality of stored computing bits, the string current signal has a second current level.
10 . The memory device of claim 9 , wherein when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, each of the plurality of first switch elements is turned on.
11 . The memory device of claim 9 , wherein the first difference is smaller than the second difference, and the first current level is larger than the second current level.
12 . The memory device of claim 9 , wherein the plurality of second switch elements comprise: a third switch element configured to have a first threshold voltage level when the plurality of stored computing bits has a first store value, and configured to have a second threshold voltage level larger than the first threshold voltage level when the plurality of stored computing bits has a second store value.
13 . The memory device of claim 12 , wherein the plurality of second switch elements further comprise: a fourth switch element configured to have the first threshold voltage level when the plurality of stored computing bits has the second store value, and configured to have the second threshold voltage level when the plurality of stored computing bits has a third store value, wherein the third store value is larger than each of the second store value and the first store value.
14 . The memory device of claim 13 , wherein the plurality of second switch elements further comprise: a fifth switch element configured to have the first threshold voltage level when the plurality of stored computing bits has the third store value, and configured to have the second threshold voltage level when the plurality of stored computing bits has a fourth store value, wherein the fourth store value is larger than the third store value.
15 . The memory device of claim 13 , wherein the plurality of second switch elements further comprise: a fifth switch element configured to have the second threshold voltage level when the plurality of stored computing bits has the first store value, configured to have the first threshold voltage level when the plurality of stored computing bits has the second store value, and configured to have the first threshold voltage level when the plurality of stored computing bits has the third store value.
16 . The memory device of claim 15 , wherein the plurality of second switch elements further comprise: a sixth switch element configured to have the second threshold voltage level when the plurality of stored computing bits has the first store value, configured to have the second threshold voltage level when the plurality of stored computing bits has the second store value, and configured to have the first threshold voltage level when the plurality of stored computing bits has the third store value.
17 . A memory system, comprising a plurality of memory strings configured to generate a plurality of bit line signals, the plurality of memory strings comprising: a plurality of first memory strings configured to compare a plurality of first stored data and a plurality of input data to generate a plurality of first string current signals, and sum the plurality of first string current signals to generate a first bit line signal; and a plurality of second memory strings configured to compare a plurality of second stored data and the plurality of input data to generate a plurality of second string current signals, and sum the plurality of second string current signals to generate a second bit line signal, wherein in response to a store value of store filter bits stored in a third memory string of the plurality of first memory strings being different from an input value of input filter bits of a first input data of the plurality of input data, at least one switch element in the third memory string is turned off, and in response to a store value of store filter bits stored in a fourth memory string of the plurality of second memory strings being equal to the input value of the input filter bits of the first input data of the plurality of input data, when a difference between a store value of stored computing bits stored in the fourth memory string and an input value of input computing bits of the first input data is smaller, a current level of a third string current signal generated by the fourth memory string is larger.
18 . The memory system of claim 17 , wherein in response to a store value of store filter bits stored in a fifth memory string of the plurality of first memory strings being different from an input value of input filter bits of a second input data of the plurality of input data, at least one switch element in the fifth memory string is turned off.
19 . The memory system of claim 18 , wherein in response to a store value of store filter bits stored in a sixth memory string of the plurality of second memory strings being equal to the input value of the input filter bits of the second input data of the plurality of input data, when a difference between a store value of stored computing bits stored in the sixth memory string and an input value of input computing bits of the second input data is smaller, a current level of a fourth string current signal generated by the sixth memory string is larger.
20 . The memory system of claim 19 , wherein in response to a first difference being between the store value of the stored computing bits stored in the fourth memory string and the input value of the input computing bits of the first input data, the third string current signal has a first current level, in response to a second difference being between the store value of the stored computing bits stored in the sixth memory string and the input value of the input computing bits of the second input data, the fourth string current signal has a second current level, the first difference is larger than the second difference, and the first current level is smaller than the second current level.

Description

BACKGROUND Technical Field The present disclosure relates to a memory technique. More particularly, the present disclosure relates to a memory device and a memory system. Description of Related Art Existing in-memory searching (IMS) functions can compare input data and stored data to perform matching operations. However, the existing IMS functions consume relatively high chip power. Thus, techniques associated with the designing a memory device that can save the chip power and perform IMS functions are important issues in the field. SUMMARY The present disclosure provides a memory device. The memory device includes a memory string configured to generate a string current signal. The memory string includes a first string portion and a second string portion. The first string portion configured to store at least one stored filter bit, and compare at least one input filter bit with the at least one stored filter bit. The second string portion coupled in series with the first string portion, and configured to store a plurality of stored computing bits, and compare a plurality of input computing bits with the plurality of stored computing bits. When an input value of the at least one input filter bit is different from a stored value of the at least one stored filter bit, the string current signal has a first current level, when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and an input value of the plurality of input computing bits has a first difference with a stored value of the plurality of stored computing bits, the string current signal has a second current level, and when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a second difference with the stored value of the plurality of stored computing bits, the string current signal has a third current level. In some embodiments, each of the second current level and the third current level is larger than the first current level, and the second current level and the third current level are different from each other. In some embodiments, the first difference is smaller than the second difference, and the second current level is larger than the third current level. In some embodiments, when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a third difference with the stored value of the plurality of stored computing bits, the string current signal has a fourth current level, the third difference is larger than each of the first difference and the second difference, and the fourth current level is smaller than each of the second current level and the third current level. In some embodiments, when the input value of the at least one input filter bit is equal to the stored value of the at least one stored filter bit, and the input value of the plurality of input computing bits has a fourth difference with the stored value of the plurality of stored computing bits, the string current signal has a fifth current level, the fourth difference is larger than the first difference and the second difference, and the fifth current level is smaller than the fourth current level, and is larger than the first current level. In some embodiments, when the first string portion comprising a plurality of switch elements, when the store value of the at least one stored filter bit has a range, each of the plurality of switch elements has a first threshold voltage level. In some embodiments, when the store value of the at least one stored filter bit has the range and the at least one input filter bit has a first input value, each of the plurality of switch elements is turned on, and when the store value of the at least one stored filter bit has the range and the at least one input filter bit has a second input value different from the first input value, each of the plurality of switch elements is turned on. In some embodiments, the plurality of switch elements are configured to receive a plurality of word line signals, respectively, when the input value of the at least one input filter bit has the range, each of the plurality of word line signals has a first voltage level, and each of the plurality of switch elements is turned on. The present disclosure provides a memory device. The memory device includes a memory string configured to generate a string current signal. The memory string includes a first string portion and a second string portion. The first string portion includes a plurality of first switch elements, and is configured to store at least one stored filter bit. The second string portion includes a plurality of second switch elements coupled in series with the plurality of first switch elements, and is configured to store a plurality o