US-20260128105-A1 - SEMICONDUCTOR DEVICES AND METHODS OF OPERATING THEREOF, SYSTEMS, AND COMPUTER-READABLE STORAGE MEDIA

Abstract

An example semiconductor device includes memory banks and a peripheral circuit. The peripheral circuit is configured to provide a first voltage to the bit line and sense a current on the bit line during a first read stage of a first memory bank and provide a second voltage to the bit line and sense a current on the bit line during a second read stage of a second memory bank. The first memory bank and the second memory bank are arranged along a direction from a first end of the bit line pointing to a second end of the bit line. The first end includes a node where the bit line is coupled to a page buffer or a bit line driver, The second voltage is greater than the first voltage, and/or a sense duration of the second read stage is greater than that of the first read stage.

Inventors

• Yuanyuan Min
• Wendong Wang
• Feng Xu
• Lei Jin
• ZongLiang Huo
• Jianquan Jia

Assignees

• YANGTZE MEMORY TECHNOLOGIES HOLDING CO., LTD.

Dates

Publication Date

20260507

Application Date

20250924

Priority Date

20241106

Claims (20)

1. 1 . A semiconductor device, comprising: a plurality of memory banks; and a peripheral circuit coupled to the plurality of memory banks through a bit line and configured to: provide a first voltage to the bit line and sense a current on the bit line during a first read stage of a first memory bank of the plurality of memory banks; and provide a second voltage to the bit line and sense a current on the bit line during a second read stage of a second memory bank of the plurality of memory banks, wherein the first memory bank and the second memory bank are arranged along a direction from a first end of the bit line pointing to a second end of the bit line, the first end is a node where the bit line is coupled to a page buffer or a bit line driver, the second read stage is different from the first read stage, and the second voltage is greater than the first voltage, and/or a sense duration of the second read stage is greater than a sense duration of the first read stage.
2. 2 . The semiconductor device of claim 1 , wherein the peripheral circuit comprises: a voltage generation circuit configured to generate an initial voltage, wherein the initial voltage is greater than or equal to the second voltage; and a voltage regulation circuit coupled to the voltage generation circuit and the bit line, respectively, and configured to: regulate the initial voltage to the first voltage during the first read stage; and regulate the initial voltage to the second voltage during the second read stage.
3. 3 . The semiconductor device of claim 2 , wherein the voltage regulation circuit includes a variable resistor.
4. 4 . The semiconductor device of claim 1 , wherein the peripheral circuit comprises: a voltage generation circuit coupled to the bit line and configured to: generate the first voltage during the first read stage; and generate the second voltage during the second read stage.
5. 5 . The semiconductor device of claim 1 , wherein in a case where the sense duration of the second read stage is greater than the sense duration of the first read stage, a first reference current corresponding to the first read stage is greater than a second reference current corresponding to the second read stage.
6. 6 . The semiconductor device of claim 5 , wherein the peripheral circuit is further configured to: generate a first read result based on a sensed current on the bit line during the first read stage and the first reference current; and generate a second read result based on a sensed current on the bit line during the second read stage and the second reference current.
7. 7 . The semiconductor device of claim 1 , wherein the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in different memory bank groups, respectively.
8. 8 . The semiconductor device of claim 1 , wherein the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in the same memory bank group.
9. 9 . The semiconductor device of claim 1 , wherein the peripheral circuit is further configured to: apply corresponding input voltages to a plurality of first selection lines coupled to the first memory bank during the first read stage respectively; and apply corresponding input voltages to a plurality of second selection lines coupled to the second memory bank during the second read stage respectively.
10. 10 . The semiconductor device of claim 1 , wherein the semiconductor device comprises a three-dimensional NAND memory device.
11. 11 . A method of operating a semiconductor device, comprising: providing a first voltage to a bit line coupled to a plurality of memory banks and sensing a current on the bit line during a first read stage of a first memory bank of the plurality of memory banks; and providing a second voltage to the bit line and sensing a current on the bit line during a second read stage of a second memory bank of the plurality of memory banks, wherein the first memory bank and the second memory bank are arranged along a direction from a first end of the bit line pointing to a second end of the bit line, the first end is a node where the bit line is coupled to a page buffer or a bit line driver, the second read stage is different from the first read stage, and the second voltage is greater than the first voltage, and/or a sense duration of the second read stage is greater than a sense duration of the first read stage.
12. 12 . The method of claim 11 , further comprising: generating an initial voltage, wherein the initial voltage is greater than or equal to the second voltage; regulating the initial voltage to the first voltage during the first read stage; and regulating the initial voltage to the second voltage during the second read stage.
13. 13 . The method of claim 11 , further comprising: generating the first voltage during the first read stage; and generating the second voltage during the second read stage.
14. 14 . The method of claim 11 , wherein in a case where the sense duration of the second read stage is greater than the sense duration of the first read stage, a first reference current corresponding to the first read stage is greater than a second reference current corresponding to the second read stage.
15. 15 . The method of claim 14 , further comprising: generating a first read result based on a sensed current on the bit line during the first read stage and the first reference current; and generating a second read result based on a sensed current on the bit line during the second read stage and the second reference current.
16. 16 . The method of claim 11 , wherein the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in different memory bank groups, respectively.
17. 17 . The method of claim 11 , wherein the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in the same memory bank group.
18. 18 . The method of claim 11 , further comprising: applying corresponding input voltages to a plurality of first selection lines coupled to the first memory bank during the first read stage respectively; and applying corresponding input voltages to a plurality of second selection lines coupled to the second memory bank during the second read stage respectively.
19. 19 . A system, comprising: at least one semiconductor device, comprising: a plurality of memory banks; and a peripheral circuit coupled to the plurality of memory banks through a bit line and configured to: provide a first voltage to the bit line and sense a current on the bit line during a first read stage of a first memory bank of the plurality of memory banks; and provide a second voltage to the bit line and sense a current on the bit line during a second read stage of a second memory bank of the plurality of memory banks, wherein the first memory bank and the second memory bank are arranged along a direction from a first end of the bit line pointing to a second end of the bit line, the first end is a node where the bit line is coupled to a page buffer or a bit line driver, the second read stage is different from the first read stage, and the second voltage is greater than the first voltage, and/or a sense duration of the second read stage is greater than sense duration of the first read stage; and a controller coupled to the semiconductor device and configured to send input data to the semiconductor device and receive an operation result of the semiconductor device.
20. 20 . The system of claim 19 , wherein the peripheral circuit comprises: a voltage generation circuit configured to generate an initial voltage, wherein the initial voltage is greater than or equal to the second voltage; and a voltage regulation circuit coupled to the voltage generation circuit and the bit line, respectively, and configured to: regulate the initial voltage to the first voltage during the first read stage; and regulate the initial voltage to the second voltage during the second read stage.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application claims the benefit of priority to China Application No. 202411579738.8, filed on Nov. 6, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD Examples of the present disclosure relate to the field of semiconductor technology, including but not limited to semiconductor devices, methods of operating a semiconductor device, and systems. BACKGROUND In the classic Von Neumann computation architecture, a memory device and processor are separated, between which data is transmitted through a data bus. When executing a command, the processor first reads data from the memory device, processes it, and then writes the updated data back to the memory device. Frequent data movement brings huge power consumption and time overhead. In addition, due to the limited bandwidth of the memory device, the processing speed of the processor is limited by the access speed of the memory device, which greatly affects computing performance. With the rise of applications such as big data and artificial intelligence, the processing of massive amounts of data has made the bottleneck of Von Neumann computation architecture increasingly prominent. SUMMARY According to a first aspect of examples of the present disclosure, a semiconductor device is provided, including: a plurality of memory banks; and a peripheral circuit coupled to the plurality of memory banks through a bit line. The peripheral circuit is configured to: provide a first voltage to the bit line and sense a current on the bit line during a first read stage of a first memory bank of the plurality of memory banks; and provide a second voltage to the bit line and sense a current on the bit line during a second read stage of a second memory bank of the plurality of memory banks, wherein the first memory bank and the second memory bank are arranged along a direction from a first end of the bit line pointing to a second end of the bit line, the first end is a node where the bit line is coupled to a page buffer or a bit line driver, the second read stage is different from the first read stage, and the second voltage is greater than the first voltage, and/or a sense duration of the second read stage is greater than a sense duration of the first read stage. In some examples, the peripheral circuit includes: a voltage generation circuit configured to generate an initial voltage, wherein the initial voltage is greater than or equal to the second voltage; and a voltage regulation circuit coupled to the voltage generation circuit and the bit line, respectively, and configured to regulate the initial voltage to the first voltage during the first read stage and regulate the initial voltage to the second voltage during the second read stage. In some examples, the voltage regulation circuit includes a variable resistor. In some examples, the peripheral circuit includes a voltage generation circuit coupled to the bit line. The voltage generation circuit is configured to: generate the first voltage during the first read stage; and generate the second voltage during the second read stage. In some examples, in a case where a sense duration of the second read stage is greater than a sense duration of the first read stage, a first reference current corresponding to the first read stage is greater than a second reference current corresponding to the second read stage. In some examples, the peripheral circuit is further configured to: generate a first read result based on a sensed current on the bit line during the first read stage and the first reference current; and generate a second read result based on a sensed current on the bit line during the second read stage and the second reference current. In some examples, the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in different memory bank groups, respectively. In some examples, the plurality of memory banks coupled to the bit line form a plurality of memory bank groups, wherein the first memory bank and the second memory bank are in the same memory bank group. In some examples, the peripheral circuit is further configured to: apply corresponding input voltages to a plurality of first selection lines coupled to the first memory bank during the first read stage; and apply corresponding input voltages to a plurality of second selection lines coupled to the second memory bank during the second read stage. In some examples, the semiconductor device includes a three-dimensional NAND memory device. According to a second aspect of examples of the present disclosure, a method of operating a semiconductor device is provided, including: providing a first voltage to a bit line coupled to a plurality of memory banks and sensing a current on the bit line during a first read stage of a first memory bank of the plurality of memory banks; and providing a se