US-20260128106-A1 - NON-VOLATILE MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND STORAGE DEVICE INCLUDING THE SAME

US20260128106A1US 20260128106 A1US20260128106 A1US 20260128106A1US-20260128106-A1

Abstract

A non-volatile memory device may include a memory cell array including a memory cell array including a plurality of first memory cells connected to a first wordline, a voltage generator configured to provide a plurality of integrity checking voltages to a first integrity checking line electrically connected to the first wordline, and a control logic circuit configured to receive a residual voltage of the first wordline from the first integrity checking line in response to provision of the plurality of integrity checking voltages to the first integrity checking line.

Inventors

Sang-In PARK

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250916
Priority Date: 20241106

Claims (20)

1 . A non-volatile memory device, comprising: a memory cell array including a plurality of first memory cells connected to a first wordline; a voltage generator configured to provide a plurality of integrity checking voltages to a first integrity checking line electrically connected to the first wordline; and a control logic circuit configured to receive a residual voltage of the first wordline from the first integrity checking line in response to provision of the plurality of integrity checking voltages to the first integrity checking line.
2 . The non-volatile memory device of claim 1 , wherein: the memory cell array further includes a plurality of second memory cells connected to a second wordline disposed adjacent to the first wordline, and the voltage generator is configured to provide the plurality of integrity checking voltages to the first integrity checking line in response to completion of a memory operation for the plurality of second memory cells.
3 . The non-volatile memory device of claim 2 , wherein: the plurality of integrity checking voltages includes sequentially higher first to nth integrity checking voltages, and the voltage generator is configured to preferentially provide the nth integrity checking voltage among the plurality of integrity checking voltages to the first integrity checking line.
4 . The non-volatile memory device of claim 3 , wherein the voltage generator is configured to provide the first to nth integrity checking voltages to the first integrity checking line in the order of the nth integrity checking voltage to the first integrity checking voltage.
5 . The non-volatile memory device of claim 2 , further comprising: a voltage generator configured to generate a pass voltage, wherein the memory operation is one of a read operation or a program operation for the plurality of second memory cells, and wherein the voltage generator is configured to provide the pass voltage to the first wordline during at least a part of the memory operation.
6 . The non-volatile memory device of claim 1 , wherein the non-volatile memory device is configured to perform a charge sharing operation between a capacitance of the first integrity checking line and a capacitance of the first wordline in response to the provision of the plurality of integrity checking voltages to the first integrity checking line.
7 . The non-volatile memory device of claim 6 , wherein: the range of the capacitance of the first integrity checking line and the capacitance of the first wordline is 1 to x, and the x is a real number in the range of 75 to 125.
8 . The non-volatile memory device of claim 6 , wherein: the plurality of integrity checking voltages includes a first integrity checking voltage and a second integrity checking voltage lower than the first integrity checking voltage, the non-volatile memory device is configured to perform: a first charge sharing operation between the capacitance of the first integrity checking line and the capacitance of the first wordline in response to the provision of the first integrity checking voltage to the first integrity checking line, and a second charge sharing operation between the capacitance of the first integrity checking line and the capacitance of the first wordline in response to the provision of the second integrity checking voltage to the first integrity checking line.
9 . The non-volatile memory device of claim 8 , wherein: the control logic circuit is configured to generate a first voltage variation value of the residual voltage in response to a result of the first charge sharing operation, the control logic circuit is configured to generate a second voltage variation value of the residual voltage in response to a result of the second charge sharing operation, and the second voltage variation value is greater than the first voltage variation value.
10 . The non-volatile memory device of claim 9 , wherein the amount of power accumulation of the first integrity checking capacitance increases in response to the provision of the first integrity checking voltage to the first integrity checking line.
11 . The non-volatile memory device of claim 1 , wherein the control logic circuit includes a voltage variation value generator configured to generate a voltage variation value between a previous residual voltage of the first wordline received before provision of a first integrity checking voltage among the plurality of integrity checking voltages and a residual voltage of the first wordline received after provision of the first integrity checking voltage.
12 . The non-volatile memory device of claim 11 , wherein the voltage variation value generator includes: an operational amplifier configured to output the voltage variation value, and a sample hold circuit configured to maintain the previous residual voltage and provide the previous residual voltage to the operational amplifier.
13 . The non-volatile memory device of claim 11 , wherein the control logic circuit further includes a comparator configured to: compare the voltage variation value with a predetermined reference voltage, and output a pass/fail signal in response to a result of the comparison.
14 . A method of operating a non-volatile memory device, the method comprising: performing a memory operation for a target wordline; providing a first integrity checking voltage to an integrity checking line electrically connected to an adjacent wordline disposed adjacent to the target wordline, in response to completion of the memory operation; performing a first charge sharing operation for sharing charge between a capacitance of the adjacent wordline and a capacitance of the integrity checking line accumulated by the first integrity checking voltage; generating a first voltage variation value of a residual voltage of the adjacent wordline in response to the first charge sharing operation; and detecting a determination residual voltage for the adjacent wordline based on the first voltage variation value.
15 . The method of claim 14 , further comprising: determining the integrity of the adjacent wordline based on the determination residual voltage and a predetermined threshold voltage.
16 . The method of claim 15 , further comprising: outputting a status signal of the adjacent wordline to outside the non-volatile memory device in response to a determination of badness of the adjacent wordline.
17 . The method of claim 14 , further comprising: providing a second integrity checking voltage lower than the first integrity checking voltage to the integrity checking line after providing the first integrity checking voltage; performing a second charge sharing operation for sharing charges between the capacitance of the adjacent wordline and the capacitance of the integrity checking line accumulated by the second integrity checking voltage; and generating a second voltage variation value in response to the second charge sharing operation, wherein the determination residual voltage is detected based on the first and second voltage variation values.
18 . The method of claim 14 , wherein the generating of the first voltage variation value includes: discharging the capacitance of the integrity checking line and receiving a residual voltage of the adjacent wordline.
19 . A storage device, comprising: a non-volatile memory device including: a memory cell array including a plurality of first memory cells connected to a first wordline, and a control logic circuit configured to detect a determination residual voltage for the first wordline through a first integrity checking line electrically connected to the first wordline, and output a status signal for the first wordline based on the determination residual voltage; and a storage controller configured to perform a replacement operation for the first wordline based on the status signal.
20 . The storage device of claim 19 , wherein: the non-volatile memory device further includes a voltage generator configured to provide a plurality of integrity checking voltages to the first integrity checking line, and the control logic circuit is configured to receive a residual voltage of the first wordline from the first integrity checking line and detect the determination residual voltage based on a voltage variation value of the residual voltage, in response to the provision of the plurality of integrity checking voltages to the first integrity checking line.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0156447, filed in the Korean Intellectual Property Office on Nov. 6, 2024, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION (a) Field of the Invention The present disclosure relates to a non-volatile memory device, a method of operating the non-volatile memory device, and a storage device including the non-volatile memory device. (b) Description of the Related Art Semiconductor memory devices may be classified into volatile memory devices and non-volatile memory devices depending on whether stored data is lost when power is cut off. A non-volatile memory device includes memory cells connected to wordlines and bitlines, and various types of voltages are applied to a plurality of wordlines while a program/read operation is performed on the memory cells. When the program/read operation is completed, a recovery operation is performed to discharge the wordlines, and if the recovery operation is not performed properly, it may cause disturbance to surrounding memory cells. Particularly, some of a plurality of wordlines may have inherent defects and may not allow the recovery operation to be performed properly, and in order to ensure the reliability of the non-volatile memory device, bad wordlines need to be screened out. SUMMARY An example embodiment provides a non-volatile memory device for selecting a bad wordline that is internally defective, and a method of operating the non-volatile memory device. An example embodiment provides a non-volatile memory device for rapidly selecting a bad wordline without leaving residual voltage, a method of operating the non-volatile memory device, and a storage device including the non-volatile memory device. According to an example embodiment, a non-volatile memory includes a memory cell array including a memory cell array including a plurality of first memory cells connected to a first wordline, a voltage generator configured to provide a plurality of integrity checking voltages to a first integrity checking line electrically connected to the first wordline, and a control logic circuit configured to receive a residual voltage of the first wordline from the first integrity checking line in response to provision of the plurality of integrity checking voltages to the first integrity checking line. According to an example embodiment, a method of operating a non-volatile memory device includes performing a memory operation for a target wordline, providing a first integrity checking voltage to an integrity checking line electrically connected to an adjacent wordline disposed adjacent to the target wordline, in response to completion of the memory operation, performing a first charge sharing operation for sharing charge between a wordline capacitance of the adjacent wordline and a capacitance of the integrity checking line accumulated by the first integrity checking voltage, generating a first voltage variation value of a residual voltage of the adjacent wordline in response to the first charge sharing operation, and detecting a determination residual voltage for the adjacent wordline based on the first voltage variation value. According to an example embodiment, a storage device includes a non-volatile memory device including a memory cell array including a plurality of first memory cells connected to a first wordline, and a control logic circuit configured to detect a determination residual voltage for the first wordline through a first integrity checking line electrically connected to the first wordline and output a status signal for the first wordline based on the determination residual voltage, and a storage controller configured to perform a replacement operation for the first wordline based on the status signal. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a storage device according to an embodiment. FIG. 2 is a block diagram illustrating a controller according to an embodiment. FIG. 3 is a block diagram illustrating a non-volatile memory device according to an embodiment. FIG. 4 illustrates a three-dimensional structure of a memory cell array according to an embodiment. FIG. 5 illustrates the connection relationship of a wordline, an integrity checking line, a voltage generator, and a control logic according to an embodiment. FIG. 6 is a circuit diagram showing a voltage variation value generator according to an embodiment. FIG. 7 is a block diagram showing a voltage variation value generator according to an embodiment. FIG. 8 is a flowchart for describing a method of operating a non-volatile memory device according to an embodiment. FIG. 9 is a timing diagram for describing a method of operating a non-volatile memory device according to an embodiment. FIGS. 10 to 16 illustrate a method of operating a non-volatile memory device according to example embodiments