US-20260128107-A1 - METHODS AND SYSTEMS TO PERFORM THRESHOLD VERIFICATION USING MULTI-LEVEL SENSING OF MEMORY CELLS

US20260128107A1US 20260128107 A1US20260128107 A1US 20260128107A1US-20260128107-A1

Abstract

Methods, systems, and devices for techniques for faster voltage threshold verification are provided. In one embodiment, a memory device comprises a memory cell and page buffer. The memory cell is coupled to a word line to receive a word voltage corresponding to a first level of the memory cell. The page buffer is coupled to a bit line associated with the memory cell. The page buffer comprises a sense amplifier configured to sense a current of the bit line. The sense amplifier is configured to determine a voltage of the sense amplifier based on the current at a first point in time that corresponds to a PV voltage of the first level. The sense amplifier is configured to determine the circuit voltage of the sense amplifier based on the current at a second point in time that corresponds to a SPPV voltage of a second level of the memory cell.

Inventors

Jisuk Kim

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260507
Application Date: 20251020

Claims (20)

1 . A memory device comprising: a memory cell coupled to a word line, the word line being configured to receive a word line voltage corresponding to a first logical level of the memory cell; and a page buffer coupled to a bit line associated with the memory cell, the page buffer comprising a sense amplifier configured to: sense a current of the bit line associated with the memory cell, the current being based on the word line voltage and a present logical level of the memory cell; determine a circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a first point in time, the first point in time corresponding to a program verify (PV) voltage of the first logical level of the memory cell; and determine the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a second point in time, the second point in time corresponding to a second pre-program verify (SPPV) voltage of a second logical level of the memory cell.
2 . The memory device of claim 1 , wherein the sense amplifier is configured to determine the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a third point in time, the third point in time corresponding to a first pre-program verify (FPPV) voltage of the first logical level of the memory cell.
3 . The memory device of claim 2 , wherein: the word line voltage comprises a first word line voltage; the memory device comprises a local controller configured to cause a second word line voltage to be applied to the word line coupled to the memory cell, the second word line voltage corresponding to the second logical level; and the sense amplifier is configured to: sense the current of the bit line associated with the memory cell, the current being based on the second word line voltage and the present logical level of the memory cell; determine the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a fourth point in time, the fourth point in time corresponding to an FPPV voltage of the second logical level of the memory cell; determine the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a fifth point in time, the fifth point in time corresponding to a PV voltage of the second logical level of the memory cell; and determine the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a sixth point in time, the sixth point in time corresponding to a SPPV voltage of a third logical level of the memory cell.
4 . The memory device of claim 2 , wherein the sense amplifier is configured to: compare the circuit voltage at the first point in time to a first threshold voltage, the first threshold voltage corresponding to the PV voltage of the first logical level; compare the circuit voltage at the second point in time to a second threshold voltage, the second threshold voltage corresponding to the SPPV voltage of the second logical level; and compare the circuit voltage at the third point in time to a third threshold voltage, the third threshold voltage corresponding to the FPPV voltage of the first logical level.
5 . The memory device of claim 4 , wherein: the circuit voltage at the first point in time being less than or equal to the first threshold voltage indicates that the first logical level is the present logical level of the memory cell and that an inhibit process is to be performed; the circuit voltage at the second point in time being less than or equal to the second threshold voltage indicates that a general process to verify the present logical level of the memory cell is to be performed; the circuit voltage at the second point in time being greater than the second threshold voltage indicates that a first speed-down process to verify the present logical level of the memory cell is to be performed; and the circuit voltage at the third point in time being less than or equal to the third threshold voltage indicates that a second speed-down process to verify the present logical level of the memory cell is to be performed.
6 . The memory device of claim 5 , wherein the memory device comprises a local controller configured to: cause the inhibit process to be performed comprising causing a bit line voltage being applied to the bit line to be decreased so as to inhibit the memory cell from being programmed; cause the general process to be performed comprising causing the bit line voltage to be decreased by a general amount; cause the first speed-down process to be performed comprising causing the bit line voltage to be decreased by a first speed-down amount, the first speed-down amount being less than the general amount; and cause the second speed-down process to be performed comprising causing the bit line voltage to be decreased by a second speed-down amount, the second speed-down amount being less than the first speed-down amount.
7 . The memory device of claim 4 , wherein: the page buffer comprises a sense amplifier register, a cache register, and an additional register; and the sense amplifier is configured to: store information corresponding to the SPPV voltage in the sense amplifier register; cause information corresponding to the FPPV voltage to be stored in at least one of the cache register or the additional register; and cause information corresponding to the PV voltage to be stored in at least one of the cache register or the additional register.
8 . The memory device of claim 1 , wherein: the memory device comprises a local controller and a regulator, the regulator being coupled to the memory cell via the word line; the local controller is configured to cause the regulator to apply the word line voltage at a voltage level corresponding to the first logical level; and the circuit voltage is determined at the second point in time to permit information corresponding to the SPPV voltage of the second logical level to be determined using the word line voltage at the voltage level corresponding to the first logical level.
9 . A memory device comprising: a word line configured to receive a word line voltage corresponding to a first logical level of a plurality of memory cells; a plurality of bit lines; the plurality of memory cells electrically coupled to the word line and the plurality of bit lines; a regulator electrically coupled to the word line and configured to apply the word line voltage; and a page buffer electrically coupled to the plurality of memory cells via the plurality of bit lines, the page buffer comprising a sense amplifier configured to: sense a current of the plurality of bit lines, the current being based on the word line voltage and a present logical level of the plurality of memory cells; determine a circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a first point in time, the first point in time corresponding to a first pre-program verify (FPPV) voltage of the first logical level of the plurality of memory cells; determine the circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a second point in time, the second point in time corresponding to a program verify (PV) voltage of the first logical level of the plurality of memory cells; and determine the circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a third point in time, the third point in time corresponding to a second pre-program verify (SPPV) voltage of a second logical level of the plurality of memory cells.
10 . The memory device of claim 9 , wherein: the word line voltage comprises a first word line voltage; the memory device comprises a local controller configured to cause the regulator to apply a second word line voltage to be applied to the word line, the second word line voltage corresponding to the second logical level; and the sense amplifier is configured to: sense the current of the plurality of bit lines, the current being based on the second word line voltage and the present logical level of the plurality of memory cells; determine the circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a fourth point in time, the fourth point in time corresponding to an FPPV voltage of the second logical level of the plurality of memory cells; determine the circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a fifth point in time, the fifth point in time corresponding to a PV voltage of the second logical level of the plurality of memory cells; and determine the circuit voltage of the sense amplifier based on the current of the plurality of bit lines at a sixth point in time, the sixth point in time corresponding to a SPPV voltage of a third logical level of the plurality of memory cells.
11 . The memory device of claim 9 , wherein the sense amplifier is configured to: compare the circuit voltage at the first point in time to a first threshold voltage, the first threshold voltage corresponding to the FPPV voltage of the first logical level; compare the circuit voltage at the second point in time to a second threshold voltage, the second threshold voltage corresponding to the PV voltage of the first logical level; and compare the circuit voltage at the third point in time to a third threshold voltage, the third threshold voltage corresponding to the SPPV voltage of the second logical level.
12 . The memory device of claim 11 , wherein: the circuit voltage at the first point in time being less than or equal to the first threshold voltage indicates that a first speed-down process to verify the present logical level of the plurality of memory cells is to be performed; the circuit voltage at the second point in time being less than or equal to the second threshold voltage indicates that the first logical level is the present logical level of the plurality of memory cells and that an inhibit process is to be performed; the circuit voltage at the third point in time being less than or equal to the third threshold voltage indicates that a general process to verify the present logical level of the plurality of memory cells is to be performed; and the circuit voltage at the third point in time being greater than the second threshold voltage indicates that a second speed-down process to verify the present logical level of the plurality of memory cells is to be performed.
13 . The memory device of claim 12 , the memory device comprises a local controller configured to: cause the inhibit process to be performed comprising causing a plurality of bit line voltages being applied to the plurality of bit lines to be decreased so as to inhibit the plurality of memory cells from being programmed; cause the general process to be performed comprising causing the plurality of bit line voltages to be decreased by a general amount; cause the first speed-down process to be performed comprising causing the plurality of bit line voltages to be decreased by a first speed-down amount, the first speed-down amount being less than the general amount; and cause the second speed-down process to be performed comprising causing the plurality of bit line voltages to be decreased by a second speed-down amount, the second speed-down amount being greater than the first speed-down amount.
14 . The memory device of claim 9 , wherein: the memory device comprises a local controller configured to cause the regulator to apply the word line voltage at a voltage level corresponding to the first logical level; and the circuit voltage is determined at the third point in time to permit information corresponding to the SPPV voltage of the second logical level to be determined using the voltage level corresponding to the first logical level.
15 . A method comprising: sensing a current of a bit line associated with a memory cell within a memory device, the current being based on a word line voltage and a present logical level of the memory cell; determining a circuit voltage of a sense amplifier within the memory device, the circuit voltage being based on the current of the bit line associated with the memory cell at a first point in time, the first point in time corresponding to a program verify (PV) voltage of a first logical level of the memory cell; and determining the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a second point in time, the second point in time corresponding to a second pre-program verify (SPPV) voltage of a second logical level of the memory cell.
16 . The method of claim 15 further comprising determining the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a third point in time, the third point in time corresponding to a first pre-program verify (FPPV) voltage of the first logical level of the memory cell.
17 . The method of claim 16 , wherein: the word line voltage comprises a first word line voltage; the method further comprises: causing a second word line voltage to be applied to the memory cell, the second word line voltage corresponding to the second logical level; and sensing the current of the bit line associated with the memory cell, the current being based on the second word line voltage and the present logical level of the memory cell; determining the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a fourth point in time, the fourth point in time corresponding to an FPPV voltage of the second logical level of the memory cell; determining the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a fifth point in time, the fifth point in time corresponding to a PV voltage of the second logical level of the memory cell; and determining the circuit voltage of the sense amplifier based on the current of the bit line associated with the memory cell at a sixth point in time, the sixth point in time corresponding to a SPPV voltage of a third logical level of the memory cell.
18 . The method of claim 16 further comprising: comparing the circuit voltage at the first point in time to a first threshold voltage, the first threshold voltage corresponding to the PV voltage of the first logical level; comparing the circuit voltage at the second point in time to a second threshold voltage, the second threshold voltage corresponding to the SPPV voltage of the second logical level; and comparing the circuit voltage at the third point in time to a third threshold voltage, the third threshold voltage corresponding to the FPPV voltage of the first logical level.
19 . The method of claim 18 , wherein: in accordance with the circuit voltage at the first point in time being less than or equal to the first threshold voltage, the method further comprises causing a bit line voltage being applied to the memory cell to be decreased to inhibit the memory cell from the being programmed; in accordance with the circuit voltage at the second point in time being less than or equal to the second threshold voltage, the method further comprises causing the bit line voltage to be decreased by a general amount; in accordance with the circuit voltage at the second point in time being greater than the second threshold voltage, the method further comprises causing the bit line voltage to be decreased by a first speed-down amount; and in accordance with the circuit voltage at the third point in time being less than or equal to the third threshold voltage, the method further comprises causing the bit line voltage to be decreased by a second speed-down amount, the second speed-down amount being less than the first speed-down amount.
20 . The method of claim 18 further comprising: storing information corresponding to the SPPV voltage in a sense amplifier register; storing information corresponding to the FPPV voltage in at least one of a cache register or an additional register; and storing information corresponding to the PV voltage in at least one of the cache register or the additional register.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Application No. 63/717,802, filed on Nov. 7, 2024, entitled “METHODS AND SYSTEMS TO PERFORM THRESHOLD VERIFICATION USING MULTI-LEVEL SENSING OF MEMORY CELLS,” the contents of which is incorporated by reference in its entirety for all purposes. TECHNICAL FIELD This disclosure relates to one or more systems for memory, including techniques for methods and systems to perform threshold verification using multi-level sensing of memory cells. BACKGROUND Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often denoted by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any one of which may be stored. To access the stored information, the memory device may read (e.g., sense, detect, program verify, retrieve, determine, etc.) states from the memory cells. To store information, the memory device may write (e.g., program, set, assign, etc.) states to the memory cells. Information can also be erased from the memory cells and new information can be stored in the memory cells. Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells may be described in terms of volatile configurations or non-volatile configurations. Memory cells configured in a non-volatile configuration may maintain stored logic states for extended periods of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory device in communication with a memory system controller of a memory system, in accordance with examples as disclosed herein. FIGS. 2A-2C are illustrative schematics of portions of an array of memory cells in a memory device, in accordance with examples as disclosed herein. FIG. 2D illustrates an example of a memory device including multiple blocks of memory cells in accordance with examples as disclosed herein. FIG. 3 illustrates a graphical representation of a circuit voltage over a period of time during threshold verification, in accordance with examples as disclosed herein. FIG. 4 illustrates a graphical representation of example cell distributions and example verification levels that correspond to various logical levels, in accordance with examples as disclosed herein. FIG. 5 illustrates a graphical representation of cell distributions of example logical levels of three cells of an array of memory cells, in accordance with examples as disclosed herein. FIG. 6 illustrates a flowchart showing a method that supports techniques for performing threshold verification using multi-level sensing of a memory cell, in accordance with examples as disclosed herein. DETAILED DESCRIPTION Memory devices can use cell distributions of threshold voltages (Vt) corresponding to memory cells to determine a current logical level of the memory cells. The cell distributions of the threshold voltages indicate voltage levels that, when applied to select gates of corresponding memory cells programmed at particular logical levels, cause the memory cells (e.g., transistors that form the memory cells) to conduct and be read, written to, or both. For example, the threshold voltages of the memory cells programmed at a logical level of logic 010 (e.g., a lower logical lever) may be between 1.4 volts (V) and 1.8V and the threshold voltage of the memory cells programmed at a logical level of 011 (e.g., a higher logical level) may be between 1.9V and 2.3V. A memory device can verify (e.g., determine) the cell distributions of the threshold voltages by performing programming loops. For example, during each of the programming loops, a controller of the memory device causes predetermined voltages (e.g., in the form of program pulses) to be applied to word lines connected to the memory cells at different verification levels that correspond to different logical levels. These predetermined voltages are also referred to as the word line voltages. In one example, as described in greater detail below, multiple verification levels may correspond to a same logical level. Thus, a first verification level and a second verification level of the word line voltages may both correspond to a first logical lev