US-20260128108-A1 - ONE-TIME-PROGRAMMABLE MEMORY

US20260128108A1US 20260128108 A1US20260128108 A1US 20260128108A1US-20260128108-A1

Abstract

Various one-time-programmable (OTP) memory cells are disclosed. An OTP memory cell includes an additional dopant region that extends at least partially under the gate of a transistor, such as an anti-fuse transistor. The additional dopant region provides an additional current path for a read current. Alternatively, an OTP memory cell includes three transistors; an anti-fuse transistor and two select transistors. The two select transistors can be configured as a cascaded select transistor or as two separate select transistors.

Inventors

Yih Wang
Hiroki Noguchi

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date: 20260507
Application Date: 20260105

Claims (20)

1 . A memory array, comprising: a plurality of one-time-programmable (OTP) memory cells, each OTP memory cell of the plurality of OTP memory cells comprising: an anti-fuse transistor comprising a first gate, a first dopant region forming a first source/drain region, and a second dopant region forming a second source/drain region, a select transistor comprising a second gate, the second dopant region forming a third source/drain region, and a third dopant region forming a fourth source/drain region, and a fourth dopant region connecting to the first dopant region and extending at least partially beneath the first gate of the anti-fuse transistor to create an additional read-current path that overlaps the first dopant region; a bit line electrically connected to the fourth source/drain region of each of the select transistor of the plurality of OTP memory cells; and one or more dummy regions positioned between at least one set of adjacent OTP memory cells of the plurality of OTP memory cells.
2 . The memory array of claim 1 , wherein the plurality of OTP memory cells are configured with alternating gate control such that, in adjacent OTP memory cells, the first gate is coupled to respective word line program (WLP) signal lines and the second gate is coupled to respective word line read (WLR) signal lines in alternating sequences.
3 . The memory array of claim 1 , wherein a drain/source region of the anti-fuse transistor is connected to the one or more dummy regions to form a floating region.
4 . The memory array of claim 1 , wherein each of the plurality of OTP memory cells further comprises: a first contact to the first dopant region; a second contact to the second dopant region; and a conductive element connecting the first and the second contacts.
5 . The memory array of claim 4 , wherein the additional read-current path is activated with a first bias voltage applied to the first contact and a second current path is activated when the first bias voltage is applied to the second contact.
6 . The memory array of claim 1 , wherein each of the plurality of OTP memory cells further comprises a halo region between the second and the third dopant regions and adjacent the second dopant region.
7 . The memory array of claim 1 , wherein the first dopant region, the second dopant region, the third dopant region, and the fourth dopant region are formed with a dopant or dopants having a first conductivity type.
8 . A one-time-programmable (OTP) memory cell, comprising: an anti-fuse transistor comprising a first gate, a first dopant region forming a first source/drain region, and a second dopant region forming a second source/drain region, a select transistor comprising a second gate, the second dopant region forming a third source/drain region, and a third dopant region forming a fourth source/drain region, and a bit line electrically connected to the fourth source/drain region the select transistor; and one or more dummy regions positioned adjacent to the anti-fuse transistor.
9 . The OTP memory cell of claim 8 , wherein a fourth dopant region creates an additional read-current path that overlaps the first dopant region.
10 . The OTP memory cell of claim 9 , further comprising: a first contact to the first dopant region; a second contact to the second dopant region; and a conductive element connecting the first and the second contacts.
11 . The OTP memory cell of claim 10 , wherein the additional read-current path is activated with a first bias voltage applied to the first contact and a second current path is activated when the first bias voltage is applied to the second contact.
12 . The OTP memory cell of claim 8 , further comprising a halo region between the second and the third dopant regions and adjacent the second dopant region.
13 . The OTP memory cell of claim 8 , wherein the first dopant region, the second dopant region, and the third dopant region are formed with a dopant or dopants having a first conductivity type.
14 . The OTP memory cell of claim 8 , wherein the OTP memory cell is included in a plurality of OTP memory cells in a memory array.
15 . An electronic device, comprising: a processing device; and a memory array operatively connected to the processing device, the memory array comprising: a one-time-programmable (OTP) memory cell, comprising: an anti-fuse transistor comprising a first gate, a first dopant region forming a first source/drain region, and a second dopant region forming a second source/drain region, a select transistor comprising a second gate, the second dopant region forming a third source/drain region, and a third dopant region forming a fourth source/drain region, and a bit line electrically connected to the fourth source/drain region of each of the select transistor of the plurality of OTP memory cells; and one or more dummy regions positioned between at least one set of adjacent OTP memory cells of the plurality of OTP memory cells; wherein the memory array is configured with alternating gate control such that, in adjacent OTP memory cells, the first gate is coupled to respective word line program (WLP) signal lines and the second gate is coupled to respective word line read (WLR) signal lines in alternating sequence.
16 . The electronic device of claim 15 , wherein a drain/source region of the anti-fuse transistor is connected to the one or more dummy regions to form a floating region.
17 . The electronic device of claim 15 , wherein the OTP memory cell further comprises: a first contact to the first dopant region; a second contact to the second dopant region; and a conductive element connecting the first and the second contacts.
18 . The electronic device of claim 17 , wherein an additional current path that overlaps the first dopant region is activated with a first bias voltage applied to the first contact.
19 . The electronic device of claim 15 , wherein the OTP memory cell further comprises a halo region between the second and the third dopant regions and adjacent the second dopant region.
20 . The electronic device of claim 15 , wherein the first dopant region, the second dopant region, and the third dopant region are formed with a dopant or dopants having a first conductivity type.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority and is a continuation of U.S. patent application Ser. No. 18/672,623, filed May 23, 2024, which is a continuation of U.S. patent application Ser. No. 17/536,639, filed Nov. 29, 2021, now U.S. Pat. No. 12,027,220, which is a division of U.S. patent application Ser. No. 16/803,202, filed Feb. 27, 2020, now U.S. Pat. No. 11,189,356, which are hereby incorporated by reference in their entirety herein. BACKGROUND Many modern day electronic devices include electronic memory. Electronic memory is a device configured to store bits of data in respective memory cells. A memory cell is a circuit configured to store a bit of data, typically using one or more transistors. One type of an electronic memory is one-time programmable (OTP) memory. An OTP memory is a read-only memory that may be programmed (e.g., written to) only once. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: FIG. 1 illustrates a block diagram of a memory device in which aspects of the disclosure may be practiced in accordance with some embodiments; FIG. 2 depicts a schematic diagram of a first OTP memory cell in accordance with some embodiments; FIG. 3 illustrates an example implementation of the first OTP memory cell shown in FIG. 2; FIG. 4 depicts a layout of first OTP memory cells in accordance with some embodiments; FIG. 5 illustrates a schematic diagram of the first OTP memory cells shown in FIG. 4; FIG. 6 depicts an example implementation of a second OTP memory cell in accordance with some embodiments; FIG. 7 illustrates a schematic diagram of a third OTP memory cell in accordance with some embodiments; FIG. 8 depicts a layout of third OTP memory cells in accordance with some embodiments; FIG. 9 illustrates a schematic diagram of the third OTP memory cells shown in FIG. 8; FIG. 10 depicts a memory array with third OTP memory cells in accordance with some embodiments; and FIG. 11 illustrates example bias voltages for the OTP memory cells shown in FIG. 10. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “under”, “upper,” “top,” “bottom,” “front,” “back,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the Figure(s). The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. Because components in various embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration only and is in no way limiting. When used in conjunction with layers of an integrated circuit, semiconductor device, or electronic device, the directional terminology is intended to be construed broadly, and therefore should not be interpreted to preclude the presence of one or more intervening layers or other intervening features or elements. Thus, a given layer that is described herein as being formed on, over, or under, or disposed on, over, or under another layer may be separated from the latter layer by one or more additional layers. Embodiments described herein provide various one-time-programmable (OTP) memory cells. In one embodiment, the OTP memory cell includes an additional dopant region that extends under the gate of a transistor. In one embodiment, the additional dopant region extends under the gate of a word line program of an anti-fuse transistor in the OTP memory cell. The additional dopant region can minimize the diode effect, which in turn enables the memory cell current to be tightened. In another embodiment, the OTP memory cell includes three transistors, an anti-fuse transistor and two sel