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US-20260128109-A1 - READ-ONLY MEMORY WITH ONE-TRANSISTOR READ-ONLY MEMORY CELLS AND METHOD FOR WRITING READ-ONLY MEMORY CODE WITH BIT LINE LOAD OPTIMIZATION INTO READ-ONLY MEMORY

US20260128109A1US 20260128109 A1US20260128109 A1US 20260128109A1US-20260128109-A1

Abstract

A read-only memory (ROM) includes a first ROM cell, a second ROM cell, and a third ROM cell. The first ROM cell is configured to store a first data value of a ROM code, and includes a first meta-oxide-semiconductor (MOS) transistor. The second ROM cell is configured to store a second data value of the ROM code, and includes a second MOS transistor, wherein a source node of the second MOS transistor is electrically connected to a drain node of the first MOS transistor. The third ROM cell is configured to store a third data value of the ROM code, and includes a third MOS transistor, wherein a drain node of the third MOS transistor is electrically connected to a source node of the first MOS transistor.

Inventors

  • Tzu-Hsien YANG
  • Yi-Te Chiu

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260507
Application Date
20251008

Claims (20)

  1. 1 . A read-only memory (ROM) comprising: a first ROM cell, configured to store a first data value of a ROM code, wherein the first ROM cell comprises: a first meta-oxide-semiconductor (MOS) transistor, having a gate node, a source node, and a drain node; a second ROM cell, configured to store a second data value of the ROM code, wherein the second ROM cell comprises: a second MOS transistor, having a gate node, a source node, and a drain node, wherein the source node of the second MOS transistor is electrically connected to the drain node of the first MOS transistor; and a third ROM cell, configured to store a third data value of the ROM code, wherein the third ROM cell comprises: a third MOS transistor, having a gate node, a source node, and a drain node, wherein the drain node of the third MOS transistor is electrically connected to the source node of the first MOS transistor.
  2. 2 . The ROM of claim 1 , wherein the first data value is a data value of 0, the source node of the first MOS transistor is electrically connected to a reference voltage, and the drain node of the first MOS transistor is electrically connected to a bit line.
  3. 3 . The ROM of claim 1 , wherein the first data value is a data value of 0, the drain node of the first MOS transistor is electrically connected to a reference voltage, and the source node of the first MOS transistor is electrically connected to a bit line.
  4. 4 . The ROM of claim 1 , wherein the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor are electrically connected to a bit line.
  5. 5 . The ROM of claim 1 , wherein the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor are electrically connected to a reference voltage.
  6. 6 . The ROM of claim 1 , wherein the first data value is a data value of 1, one of the source node and the drain node of the first MOS transistor is floating.
  7. 7 . The ROM of claim 1 , wherein the first data value is a data value of 1, both of the source node and the drain node of the first MOS transistor are floating.
  8. 8 . The ROM of claim 1 , further comprising: a plurality of dummy cells, wherein a metal trace is routed above the plurality of dummy cells, and a reference voltage is delivered through the metal trace.
  9. 9 . A read-only memory (ROM) comprising: a first bit line; a second bit line; and a first ROM cell, configured to store a first data value of a ROM code, wherein the first ROM cell comprises: a first meta-oxide-semiconductor (MOS) transistor, having a gate node, a source node, and a drain node, wherein the drain node is electrically connected to one of the first bit line and the second bit line, and the source node is electrically connected to one of the first bit line and the second bit line; wherein the first data value is read from the first ROM cell through the first bit line and the second bit line.
  10. 10 . The ROM of claim 9 , wherein the first data value is a data value of 0, the drain node is electrically connected to one of the first bit line and the second bit line, and the source node is electrically connected to another of the first bit line and the second bit line.
  11. 11 . The ROM of claim 9 , wherein the first data value is a data value of 1, both of the drain node and the source node are electrically connected to a same bit line of the first bit line and the second bit line.
  12. 12 . The ROM of claim 9 , further comprising: a second ROM cell, configured to store a second data value of the ROM code, wherein the second ROM cell comprises: a second MOS transistor, having a gate node, a source node, and a drain node, wherein the source node of the second MOS transistor is electrically connected to the drain node of the first MOS transistor; and a third ROM cell, configured to store a third data value of the ROM code, wherein the third ROM cell comprises: a third MOS transistor, having a gate node, a source node, and a drain node, wherein the drain node of the third MOS transistor is electrically connected to the source node of the first MOS transistor.
  13. 13 . A method for writing a read-only memory (ROM) code into a ROM, comprising: determining a VIA layer design of the ROM according to the ROM code, comprising: determining a VIA layer design of a second ROM cell according to a VIA layer design of a first ROM cell and a data value to be stored in the second ROM cell, wherein the first ROM cell and the second ROM cell are adjacent ROM cells; and writing the ROM code into the ROM by manufacturing vias of the ROM according to the VIA layer design of the ROM.
  14. 14 . The method of claim 13 , wherein the first ROM cell comprises: a first meta-oxide-semiconductor (MOS) transistor, having a gate node, a source node, and a drain node; the second ROM cell comprises: a second MOS transistor, having a gate node, a source node, and a drain node; wherein a same VIA setting is shared between the drain node of the first MOS transistor and the source node of the second MOS transistor.
  15. 15 . The method of claim 13 , wherein a VIA layer design of the first ROM cell defines that the drain node of the first MOS transistor is electrically connected to a bit line, the data value to be stored in the second ROM cell is a data value of 1, and a VIA layer design of the second ROM cell defines that the drain node of the second MOS transistor is electrically connected to the bit line.
  16. 16 . The method of claim 13 , wherein a VIA layer design of the first ROM cell defines that the drain node of the first MOS transistor is electrically connected to a bit line, the data value to be stored in the second ROM cell is a data value of 0, and a VIA layer design of the second ROM cell defines that the drain node of the second MOS transistor is electrically connected to a reference voltage.
  17. 17 . The method of claim 13 , wherein a VIA layer design of the first ROM cell defines that the drain node of the first MOS transistor is electrically connected to a reference voltage, the data value to be stored in the second ROM cell is a data value of 1, and a VIA layer design of the second ROM cell defines that the drain node of the second MOS transistor is electrically connected to the reference voltage.
  18. 18 . The method of claim 13 , wherein a VIA layer design of the first ROM cell defines that the drain node of the first MOS transistor is electrically connected to a reference voltage, the data value to be stored in the second ROM cell is a data value of 0, and a VIA layer design of the second ROM cell defines that the drain node of the second MOS transistor is electrically connected to a bit line.
  19. 19 . The method of claim 13 , wherein determining the VIA layer design of the ROM according to the ROM code further comprising: checking VIA layer designs of contiguous ROM cells to determine if there are consecutive VIA settings with a same setting, wherein the same setting defines a bit line connection; and in response to determining that there are the consecutive VIA settings with the same setting, changing at least one VIA setting of the consecutive VIA settings to a new setting, wherein the new setting removes the bit line connection.
  20. 20 . The method of claim 19 , wherein the consecutive VIA settings are separated into a plurality of VIA setting groups by the at least one VIA setting, and determining the VIA layer design of the ROM according to the ROM code further comprising: applying inversion to at least one of the plurality of VIA setting groups, wherein the inversion changes each VIA setting from one of a reference voltage connection and the bit line connection to another of the reference voltage connection and the bit line connection.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/714,867, filed on Nov. 1, 2024. The content of the application is incorporated herein by reference. BACKGROUND The present invention relates to a read-only memory (ROM) design, and more particularly, to a ROM with one-transistor (1T) ROM cells and a method for writing a ROM code with bit line (BL) load optimization into the ROM. A ROM is a non-volatile memory where data is fixed during the manufacturing process and is commonly used to store a boot-up code, BIOS firmware, and device driver programs in a system on a chip (SOC). However, as an SOC design becomes more complex, a larger ROM capacity is needed. Increasing the ROM storage capacity requires a larger die area, which increases the area and the power consumption of the SOC. The conventional ROM cell is formed by 1.5 transistors, where data is stored in a VD layer located in a source node of a metal-oxide-semiconductor (MOS) transistor and is isolated by an isolation device shared between two adjacent ROM cells. These dummy isolation devices in a conventional ROM waste die area and increase BL length, causing performance degradation and increased power consumption. Thus, there is a need for an innovative ROM design with no dummy isolation devices. SUMMARY One of the objectives of the claimed invention is to provide a ROM with 1T ROM cells and a method for writing a ROM code with BL load optimization into the ROM. According to a first aspect of the present invention, an exemplary ROM is disclosed. The exemplary ROM includes a first ROM cell, a second ROM cell, and a third ROM cell. The first ROM cell is configured to store a first data value of a ROM code, and includes a first MOS transistor having a gate node, a source node, and a drain node. The second ROM cell is configured to store a second data value of the ROM code, and includes a second MOS transistor having a gate node, a source node, and a drain node, wherein the source node of the second MOS transistor is electrically connected to the drain node of the first MOS transistor. The third ROM cell is configured to store a third data value of the ROM code, and includes a third MOS transistor having a gate node, a source node, and a drain node, wherein the drain node of the third MOS transistor is electrically connected to the source node of the first MOS transistor. According to a second aspect of the present invention, an exemplary ROM is disclosed. The exemplary ROM includes a first bit line, a second bit line, and a first ROM cell. The first ROM cell is configured to store a first data value of a ROM code, and includes a first MOS transistor having a gate node, a source node, and a drain node, wherein the drain node is electrically connected to one of the first bit line and the second bit line, and the source node is electrically connected to one of the first bit line and the second bit line. The first data value is read from the first ROM cell through the first bit line and the second bit line. According to a third aspect of the present invention, an exemplary method for writing a ROM code into a ROM is disclosed. The exemplary method includes: determining a VIA layer design of the ROM according to the ROM code, and writing the ROM code into the ROM by manufacturing vias of the ROM according to the VIA layer design of the ROM. The step of determining the VIA layer design of the ROM according to the ROM code includes: determining a VIA layer design of a second ROM cell according to a VIA layer design of a first ROM cell and a data value to be stored in the second ROM cell, wherein the first ROM cell and the second ROM cell are adjacent ROM cells. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating a ROM with high density 1T ROM bit-cells according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an example of using the proposed 1T ROM cells to store data values. FIG. 3 is a layout diagram of 1T ROM cells shown in FIG. 2 according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a 1T ROM cell code mapping scheme according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a post-CVR VIA layer design of a ROM code segment according to an embodiment of the present invention. FIG. 6 is a diagram illustrating a comparison between bit line loads of the pre-CVR VIA layer design and the post-CVR VIA layer design of the same ROM code segment according to an embodiment of the present invention. FIG. 7 is a diagram illustrating operations of a DDCO scheme for additional bit line load optimization according to an embodiment of the present invention. FIG.