US-20260128111-A1 - NON-VOLATILE MEMORY DEVICE PERFORMING WRITE TRAINING

Abstract

Provided is a non-volatile memory device performing write training. The non-volatile memory device includes a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller. The plurality of memory dies include a first memory die and a second memory die each comprising non-volatile memory cells. The first memory die receives first training data from the controller in a first interval, compares the first training data with first pattern data in a second interval, and transmits a first pass/fail value regarding the first training data to the controller. The second memory die receives second training data from the controller in the second interval.

Inventors

• Seonghyeog Choi
• CHANGKYU SEOL
• Miryeong Seol
• Yuseok SONG
• Taemin LEE
• Youngdon CHOI

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20250717

Priority Date

20241101

Claims (20)

1. 1 . A non-volatile memory device comprising: a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies comprise a first memory die and a second memory die each comprising non-volatile memory cells, wherein the first memory die is configured to receive first training data from the controller in a first interval and compare the first training data with first pattern data and transmit a first pass/fail value regarding the first training data to the controller, in a second interval after the first interval, and wherein the second memory die is configured to receive second training data from the controller in the second interval.
2. 2 . The non-volatile memory device of claim 1 , wherein the first memory die further comprises a first page buffer configured to store the first training data, and wherein the second memory die further comprises a second page buffer configured to store the second training data.
3. 3 . The non-volatile memory device of claim 2 , wherein the second memory die is configured to compare the second training data with second pattern data and transmit a second pass/fail value regarding the second training data to the controller, in a third interval after the second interval.
4. 4 . The non-volatile memory device of claim 2 , wherein the first memory die is further configured to receive a first command and the first training data from the controller, and, store the first training data in the first page buffer in response to the first command.
5. 5 . The non-volatile memory device of claim 2 , wherein the first memory die is further configured to receive a second command from the controller, and compare the first training data with the first pattern data in response to the second command,.
6. 6 . The non-volatile memory device of claim 5 , wherein the first memory die further comprises: a pattern generator configured to generate the first pattern data in response to the second command; and a comparator configured to compare the first training data received from the first page buffer with the first pattern data received from the pattern generator in response to the second command.
7. 7 . The non-volatile memory device of claim 6 , wherein the pattern generator comprises a linear feedback shift register.
8. 8 . The non-volatile memory device of claim 1 , wherein the first memory die is further configured to receive a third command from the controller, and, transmit the first pass/fail value to the controller in response to the third command.
9. 9 . The non-volatile memory device of claim 1 , wherein the first training data corresponds to a first delay value, and the second training data corresponds to the first delay value, and wherein the first memory die is further configured to receive third training data corresponding to a second delay value different from the first delay value from the controller in a third interval after the second interval.
10. 10 . The non-volatile memory device of claim 9 , further comprising a data strobe pin configured to receive a data strobe signal from the controller, wherein the first training data comprises a training pattern having a delay corresponding to the first delay value with respect to the data strobe signal, and wherein the third training data comprises a training pattern having a delay corresponding to the second delay value with respect to the data strobe signal.
11. 11 . The non-volatile memory device of claim 1 , further comprising: a command/address pin configured to receive a command and an address from the controller via a command/address signal line; a data pin configured to receive data from the controller through a data signal line; and a data strobe pin configured to receive a data strobe signal from the controller via a data strobe line, wherein the first training data and the second training data are received through the data pin, and wherein the first pass/fail value is transmitted through the command/address pin.
12. 12 . The non-volatile memory device of claim 1 , further comprising: a data pin configured to receive a command, an address, and data from the controller through a data signal line; and a data strobe pin configured to receive a data strobe signal from the controller via a data strobe line, wherein the first training data and the second training data are received through the data pin, and wherein the first pass/fail value is transmitted through the data pin.
13. 13 . A non-volatile memory device comprising: a buffer chip connected to a controller through a first channel; and a plurality of memory dies connected to the buffer chip through a second channel and configured to perform a first write training between the controller and the buffer chip during a first write training interval, wherein the plurality of memory dies comprise: a first memory die configured to receive, from the controller through the buffer chip, first training data corresponding to a first delay value during a first interval of the first write training interval; and a second memory die configured to receive, from the controller through the buffer chip, second training data corresponding to a second delay value different from the first delay value during a second interval of the first write training interval, and wherein the first memory die is configured to generate a first pass/fail value for the first training data and transmit the first pass/fail value to the controller through the buffer chip, during the second interval of the first write training interval.
14. 14 . The non-volatile memory device of claim 13 , wherein the second memory die is configured to generate a second pass/fail value for the second training data and transmit the second pass/fail value to the controller through the buffer chip, after the second interval of the first write training interval.
15. 15 . The non-volatile memory device of claim 14 , wherein the first memory die comprises: a first page buffer configured to store the first training data; a first pattern generator configured to generate first pattern data; and a first comparator configured to generate the first pass/fail value by comparing the first training data with the first pattern data, and wherein the second memory die comprises: a second page buffer configured to store the second training data; a second pattern generator configured to generate second pattern data; and a second comparator configured to generate the second pass/fail value by comparing the second training data with the second pattern data.
16. 16 . The non-volatile memory device of claim 13 , wherein the plurality of memory dies are further configured to perform second write training between the buffer chip and the plurality of memory dies during a second write training interval, wherein the first memory die is further configured to receive third training data from the controller through the buffer chip during a first interval of the second write training interval, wherein the first memory die is further configured to generate a third pass/fail value regarding the third training data, and the second memory die is configured to receive fourth training data from the controller through the buffer chip, during a second interval of the second write training interval, and wherein the first memory die is configured to receive fifth training data from the controller through the buffer chip, and the second memory die is further configured to generate a fourth pass/fail value regarding the fourth training data, during a third interval of the second write training interval.
17. 17 . The non-volatile memory device of claim 16 , wherein the third training data and the fourth training data each correspond to a third delay value, and wherein the fifth training data corresponds to a fourth delay value that is different from the third delay value.
18. 18 . A non-volatile memory device comprising: a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies comprise: a first memory die comprising a first page buffer, and configured to store reference training data and first training data received from the controller in the first page buffer and generate a first pass/fail value regarding the first training data based on a result of a logical operation for the reference training data and the first training data; and a second memory die comprising a second page buffer and configured to store the reference training data and second training data received from the controller in the second page buffer and generate a second pass/fail value regarding the second training data based on a result of a logical operation for the reference training data and the second training data, and wherein, while the first memory die generates the first pass/fail value, the second memory die is configured to receive the reference training data or the second training data.
19. 19 . The non-volatile memory device of claim 18 , wherein the first memory die is further configured to: receive the reference training data and store the reference training data in a first region of the first page buffer, during a first interval; dump the reference training data stored in the first region of the first page buffer to a second region of the first page buffer, during a second interval; receive the first training data and store the first training data in the first region of the first page buffer, during a third interval; and generate the first pass/fail value by counting results of logical operations regarding the reference training data and the first training data, during a fourth interval.
20. 20 . The non-volatile memory device of claim 19 , wherein the second memory die is further configured to: receive the reference training data and store the reference training data in a first region of the second page buffer, during the fourth interval; dump the reference training data stored in the first region of the second page buffer to a second region of the second page buffer, during a fifth interval; receive the second training data and store the second training data in the first region of the second page buffer, during a sixth interval; and generate the second pass/fail value by counting results of logical operations regarding the reference training data and the second training data, during a seventh interval, and wherein the first memory die is further configured to receive third training data during the seventh interval.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0153790, filed on Nov. 1, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND One or more example embodiments of the disclosure relate to a memory device, and more particularly, to a non-volatile memory device performing write training and a method for write training of a non-volatile memory. A storage device may include a non-volatile memory and a controller that controls the non-volatile memory. Since the non-volatile memory and the controller have different operational characteristics, initialization or training may be needed during an initial operation of the storage device or the initial operation between the non-volatile memory and the controller. In particular, a training operation may be performed to ensure the reliability of data transmitted and received between the non-volatile memory and the controller. Since data is transmitted and received between the non-volatile memory and the controller based on training parameters obtained through training operations, it may be important to obtain accurate training parameters. SUMMARY One or more example embodiments of the disclosure provide a non-volatile memory device capable of reducing a write training operation time and a write training method of the non-volatile memory device. According to an aspect of the disclosure, there is provided a non-volatile memory device including a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies include a first memory die and a second memory die each including non-volatile memory cells, the first memory die is configured to receive first training data from the controller in a first interval and compare the first training data with first pattern data and transmits a first pass/fail value regarding the first training data to the controller in a second interval after the first interval, and the second memory die is configured to receive second training data from the controller in the second interval. According to another aspect of the disclosure, there is provided a non-volatile memory device including a buffer chip connected to a controller through a first channel, and a plurality of memory dies connected to the buffer chip through a second channel and configured to perform a first write training between the controller and the buffer chip during a first write training interval, wherein the plurality of memory dies include a first memory die configured to receive first training data corresponding to a first delay value from the controller through the buffer chip during a first interval of the first write training interval, and a second memory die configured to receive second training data corresponding to a second delay value different from the first delay value from the controller through the buffer chip during a second interval of the first write training interval, and the first memory die generates a first pass/fail value for the first training data and transmits the first pass/fail value to the controller through the buffer chip, during the second interval of the first write training interval. According to another aspect of the disclosure, there is provided a non-volatile memory device including a plurality of memory dies connected to a controller through a first channel and configured to perform write training based on training data received from the controller, wherein the plurality of memory dies include a first memory die including a first page buffer and configured to store reference training data and first training data received from the controller in the first page buffer and generate a first pass/fail value regarding the first training data based on a result of a logical operation for the reference training data and the first training data, and a second memory die including a second page buffer and configured to store the reference training data and second training data received from the controller in the second page buffer and generate a second pass/fail value regarding the second training data based on a result of a logical operation for the reference training data and the second training data, and, while the first memory die generates the first pass/fail value, the second memory die receives the reference training data or the second training data. According to another aspect of the disclosure, there is provided a non-volatile memory device including a plurality of memory dies connected to a controller through a first channel, wherein the plurality of memory dies include a first memory die including a first page buffer and configured to receive first training data from the controller through the first channel during a first i