Search

US-20260128112-A1 - MEMORY MIRROR SEQUENCING FOR REDUCED LATENCY IN MEMORY PATCHING

US20260128112A1US 20260128112 A1US20260128112 A1US 20260128112A1US-20260128112-A1

Abstract

Aspects of the disclosure are directed to memory mirror sequencing for memory patching. In accordance with one aspect, the disclosure includes initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters; triggering a parallel ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters; and executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern.

Inventors

  • Rajesh Kumar Tiwari
  • Mohammed Zuber P MALEK
  • Chintakrindi BHAVANA
  • Srinivasa Rao Dasari

Assignees

  • QUALCOMM INCORPORATED

Dates

Publication Date
20260507
Application Date
20241107

Claims (20)

  1. 1 . An information processing system comprising: a plurality of read only memories (ROMs) configured to store a built-in self-test (BIST) test pattern; a memory mirror sequence (MMS) controller coupled to the plurality of ROMs, the MMS controller configured to trigger a parallel read only memory (ROM) to random access memory (RAM) copy procedure to copy the BIST test pattern from the plurality of ROMs; a plurality of random access memories (RAMs) coupled to the MMS controller, the plurality of RAMs configured to receive the BIST test pattern; and a reprogramming programmable read only memory (PROM) coupled to the plurality of ROMs and the plurality of RAMs, the PROM configured to execute a memory patching process to update the BIST test pattern to generate an updated built-in self-test (BIST) test pattern.
  2. 2 . The information processing system of claim 1 , wherein the MMS controller uses one or more parallelization parameters to trigger the parallel ROM to RAM copy procedure.
  3. 3 . The information processing system of claim 2 , wherein the one or more parallelization parameters include a quantity of the plurality of ROMS used in the parallel ROM to RAM copy procedure.
  4. 4 . The information processing system of claim 3 , wherein the one or more parallelization parameters include an adjusted clock frequency used in the parallel ROM to RAM copy procedure to obtain a low latency result; and wherein the adjusted clock frequency is greater than a baseline clock frequency of the information processing system.
  5. 5 . The information processing system of claim 4 , wherein the plurality of RAMs is further configured to store the updated BIST test pattern.
  6. 6 . An apparatus comprising: means for initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters; means for triggering a parallel ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters; and means for executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern.
  7. 7 . The apparatus of claim 6 , further comprising: means for performing a plurality of built-in self-test (BIST) sequences using the updated BIST test pattern; means for validating a performance of the plurality of BIST sequences; and means for reporting a built-in self-test (BIST) status.
  8. 8 . The apparatus of claim 7 , further comprising: means for determining if a memory patch for a read only memory (ROM) in an information processing system is required; and means for triggering a system built-in self-test (BIST) operation on the information processing system.
  9. 9 . A method comprising: initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters; triggering a parallel ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters; and executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern.
  10. 10 . The method of claim 9 , wherein the one or more parallelization parameters are used in the parallel ROM to RAM copy procedure over a plurality of read only memories (ROMs).
  11. 11 . The method of claim 9 , wherein the one or more parallelization parameters include a quantity of read only memories (ROMs) used simultaneously in the parallel ROM to RAM copy procedure.
  12. 12 . The method of claim 9 , wherein the one or more parallelization parameters include an adjusted clock frequency.
  13. 13 . The method of claim 12 , wherein the adjusted clock frequency is greater than a baseline clock frequency of an information processing system.
  14. 14 . The method of claim 13 , further comprising using the adjusted clock frequency in the parallel ROM to RAM copy procedure to obtain a low latency result.
  15. 15 . The method of claim 9 , wherein the MMS controller manages the memory patching process by using the one or more parallelization parameters.
  16. 16 . The method of claim 9 , further comprising performing a plurality of built-in self-test (BIST) sequences using the updated BIST test pattern.
  17. 17 . The method of claim 16 , further comprising: validating a performance of the plurality of BIST sequences; and reporting a built-in self-test (BIST) status.
  18. 18 . The method of claim 17 , further comprising determining if a memory patch for a read only memory (ROM) in an information processing system is required.
  19. 19 . The method of claim 18 , further comprising triggering a system built-in self-test (BIST) operation on the information processing system.
  20. 20 . The method of claim 19 , further comprising: initiating a power ON operation for the information processing system; and initiating a primary boot load (PBL) operation for the information processing system.

Description

TECHNICAL FIELD This disclosure relates generally to the field of automotive electronics circuits, and, in particular, to memory mirror sequencing for memory patching. in automotive electronics circuits. BACKGROUND Automotive electronics circuits may include logical built-in self-test (LBIST) circuitry for diagnostic testing. The LBIST circuitry may require a plurality of test pattern data to be loaded into random access memory (RAM) as a test stimulus. In some scenarios, the plurality of test pattern data may need to be copied from a read only memory (ROM) to the RAM to accommodate any post manufacturing design updates. The ROM to RAM copy process incurs significant latency so a memory mirror sequencer implementation to perform the ROM to RAM copy process may be used to reduce copy process latency. SUMMARY The following presents a simplified summary of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later. In one aspect, the disclosure provides memory mirror sequencing for memory patching. Accordingly, the present disclosure discloses an information processing system including: a plurality of read only memories (ROMs) configured to store a built-in self-test (BIST) test pattern; a memory mirror sequence (MMS) controller coupled to the plurality of ROMs, the MMS controller configured to trigger a parallel read only memory (ROM) to random access memory (RAM) copy procedure to copy the BIST test pattern from the plurality of ROMs; a plurality of random access memories (RAMs) coupled to the MMS controller, the plurality of RAMs configured to receive the BIST test pattern; and a reprogramming programmable read only memory (PROM) coupled to the plurality of ROMs and the plurality of RAMs, the PROM configured to execute a memory patching process to update the BIST test pattern to generate an updated built-in self-test (BIST) test pattern. In one example, the MMS controller uses one or more parallelization parameters to trigger the parallel ROM to RAM copy procedure. In one example, the one or more parallelization parameters include a quantity of the plurality of ROMS used in the parallel ROM to RAM copy procedure. In one example, the one or more parallelization parameters include an adjusted clock frequency used in the parallel ROM to RAM copy procedure to obtain a low latency result; and wherein the adjusted clock frequency is greater than a baseline clock frequency of the information processing system. In one example, the plurality of RAMs is further configured to store the updated BIST test pattern. Another aspect of the disclosure provides an apparatus including: means for initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters; means for triggering a parallel ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters; and means for executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern. In one example, the apparatus further includes: means for performing a plurality of built-in self-test (BIST) sequences using the updated BIST test pattern; means for validating a performance of the plurality of BIST sequences; and means for reporting a built-in self-test (BIST) status. In one example, the apparatus further includes: means for determining if a memory patch for a read only memory (ROM) in an information processing system is required; and means for triggering a system built-in self-test (BIST) operation on the information processing system. Another aspect of the disclosure provides a method including: initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters; triggering a parallel ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters; and executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern. In one example, the one or more parallelization parameters is used in the parallel ROM to RAM copy procedure over a plurality of read only memories (ROMs). In one example, the one or more paralleliza