US-20260128113-A1 - MEMORY, STORAGE DEVICE, AND MEMORY OPERATION METHOD

US20260128113A1US 20260128113 A1US20260128113 A1US 20260128113A1US-20260128113-A1

Abstract

A memory includes: multiple data storage blocks and a check code storage block; and a data check circuit, configured to: respectively obtain stored data and a corresponding first check code from the multiple data storage blocks and the check code storage block, and determine, in response to a received mode selection signal, whether to perform a data check operation. The data check circuit is further configured to: perform data check on the stored data based on the first check code, and output the stored data obtained after the data check as first read data, when the mode selection signal indicates that the memory is in an on-die check mode; or directly output the stored data and the first check code as second read data when the mode selection signal indicates that the memory is in an off-die check mode.

Inventors

Kanyu Cao
Zequn Huang
Hongwen Li
Enpeng Gao

Assignees

CXMT Corporation

Dates

Publication Date: 20260507
Application Date: 20251218
Priority Date: 20241018

Claims (19)

1 . A memory, comprising: a plurality of data storage blocks and a check code storage block; and a data check circuit, configured to: respectively obtain stored data and a corresponding first check code from the plurality of data storage blocks and the check code storage block, and determine, in response to a received mode selection signal, whether to perform a data check operation; the data check circuit being further configured to: perform data check on the stored data based on the first check code, and output the stored data obtained after the data check as first read data, when the mode selection signal indicates that the memory is in an on-die check mode; or directly output the stored data and the first check code as second read data when the mode selection signal indicates that the memory is in an off-die check mode; the first check code in the second read data being employed by an external memory controller to perform a data check operation on the stored data.
2 . The memory according to claim 1 , wherein the memory further comprises: an input/output circuit, configured to: receive the mode selection signal, and serialize the received first read data based on a first burst length and then generate a plurality of first output data strings to be output to a plurality of data ports, when the mode selection signal indicates that the memory is in the on-die check mode; or serialize the received second read data based on a second burst length and then generate a plurality of second output data strings to be output to the plurality of data ports, when the mode selection signal indicates that the memory is in the off-die check mode; the first burst length being less than the second burst length.
3 . The memory according to claim 2 , wherein each of the first output data strings comprises a part of the stored data that is serially output, and each of the second output data strings comprises a part of the stored data that is serially output and a part of the first check code.
4 . The memory according to claim 2 , wherein the input/output circuit is further configured to: receive an extended function indication signal, and serialize the received second read data and first extended data based on a third burst length and then generate a plurality of third output data strings to be output to the plurality of data ports, when the mode selection signal indicates that the memory is in the off-die check mode and the extended function indication signal indicates that the memory enables an extended function; each of the third output data strings comprising a part of the stored data that is serially output, a part of the first check code, and a part of the first extended data.
5 . The memory according to claim 2 , wherein the input/output circuit is further configured to: parallelize a first input data string of a first burst length received from each of the data ports and then generate first write data to be output to the data check circuit, when the mode selection signal indicates that the memory is in the on-die check mode; or parallelize a second input data string of a second burst length received from each of the data ports and then generate second write data to be output to the data check circuit, when the mode selection signal indicates that the memory is in the off-die check mode; the first write data comprising to-be-stored data, the second write data comprising the to-be-stored data and a corresponding second check code, the first input data string comprising a part of the to-be-stored data that is serially input, and the second input data string comprising a part of the to-be-stored data that is serially input and a part of the second check code.
6 . The memory according to claim 5 , wherein the data check circuit is further configured to: encode the to-be-stored data in the received first write data to generate a corresponding third check code, and respectively store the to-be-stored data and the third check code in the plurality of data storage blocks and the check code storage block, when the mode selection signal indicates that the memory is in the on-die check mode; or respectively store the to-be-stored data in the received second write data and the second check code in the plurality of data storage blocks and the check code storage block when the mode selection signal indicates that the memory is in the off-die check mode.
7 . The memory according to claim 4 , wherein the input/output circuit is further configured to: receive an extended function indication signal, and parallelize a third input data string of a third burst length received from each of the data ports and then generate third write data to be output to the data check circuit, when the mode selection signal indicates that the memory is in the off-die check mode and the extended function indication signal indicates that the memory enables an extended function; the third write data comprising the to-be-stored data, the corresponding second check code, and second extended data, and the third input data string comprising a part of the to-be-stored data that is serially input, a part of the second check code, and a part of the second extended data.
8 . The memory according to claim 2 , wherein the memory further comprises: a data transmission circuit, connected between the data check circuit and the input/output circuit, the data transmission circuit being configured to: transmit the first read data or the second read data from the data check circuit to the input/output circuit, and transmit the first write data or the second write data from the input/output circuit to the data check circuit.
9 . The memory according to claim 8 , wherein the input/output circuit comprises a data conversion circuit, the data conversion circuit comprises a plurality of data conversion subcircuits in a one-to-one correspondence with the plurality of data ports, and each of the data conversion subcircuits comprises a serializer and a parallelizer; the serializer is separately coupled to the data transmission circuit and the corresponding data port, and is configured to: serialize, based on the first burst length, a part of the stored data received from the data transmission circuit and then generate the first output data string to be output to the corresponding data port, when the mode selection signal indicates that the memory is in the on-die check mode; or serialize, based on the second burst length, a part of the stored data received from the data transmission circuit and a part of the first check code and then generate the second output data string to be output to the corresponding data port, when the mode selection signal indicates that the memory is in the off-die check mode; and the parallelizer is separately coupled to the data transmission circuit and the corresponding data port, and is configured to: parallelize the first input data string received from the corresponding data port and then generate a part of the first write data to be output to the data transmission circuit, when the mode selection signal indicates that the memory is in the on-die check mode; or parallelize the second input data string received from the corresponding data port and then generate a part of the second write data to be output to the data transmission circuit, when the mode selection signal indicates that the memory is in the off-die check mode.
10 . The memory according to claim 9 , wherein the input/output circuit further comprises a first in first out register and a data driver; the first in first out register is coupled between the data transmission circuit and the data conversion circuit, and is configured to: receive and cache the first read data or the second read data from the data transmission circuit during a read operation performed by the memory; and receive and cache the parallelized first write data or the parallelized second write data from the data conversion circuit during a write operation performed by the memory; and the data driver is coupled between the data conversion circuit and the plurality of data ports, and is configured to: receive the plurality of serialized first output data strings or the plurality of serialized second output data strings from the data conversion circuit and drive output to the plurality of data ports, during a read operation performed by the memory; and receive the plurality of corresponding first input data strings or the plurality of corresponding second input data strings through the plurality of data ports and drive output to the data conversion circuit, during a write operation performed by the memory.
11 . The memory according to claim 8 , wherein the data transmission circuit comprises a stored data transmission bus and a check code transmission bus; the stored data transmission bus is configured to transmit the stored data or the to-be-stored data; and the check code transmission bus is configured to: receive the mode selection signal, and transmit the first check code or the second check code when the mode selection signal indicates that the memory is in the off-die check mode; or be disabled when the mode selection signal indicates that the memory is in the on-die check mode.
12 . The memory according to claim 8 , wherein the data transmission circuit further comprises an extended data bus; the extended data bus being configured to: receive the mode selection signal and the extended function indication signal, and transmit the first extended data or the second extended data when the mode selection signal indicates that the memory is in the off-die check mode and the extended function indication signal indicates that the memory is in a state in which the extended function is enabled; otherwise, the extended data bus being disabled.
13 . A storage device, comprising at least one storage channel, each of the storage channel comprising a plurality of memories according to claim 1 .
14 . An operation method for a memory, the memory comprising a plurality of data storage blocks and a check code storage block, and the operation method comprising: respectively obtaining stored data and a corresponding first check code from the plurality of data storage blocks and the check code storage block; determining a check mode of the memory in response to a mode selection signal; and performing data check on the stored data based on the first check code and outputting the stored data obtained after the data check as first read data, when the mode selection signal indicates that the memory is in an on-die check mode; or directly outputting the stored data and the first check code as second read data when the mode selection signal indicates that the memory is in an off-die check mode; the first check code in the second read data being employed by an external memory controller to perform a data check operation on the stored data.
15 . The operation method according to claim 14 , wherein the operation method further comprises: outputting the first read data or the second read data from the memory through a plurality of data ports after being serialized; the first read data being serialized based on a first burst length, and then a plurality of first output data strings to be output through the plurality of data ports being generated, when the memory is in the on-die check mode; or the second read data being serialized based on a second burst length, and then a plurality of second output data strings to be output through the plurality of data ports being generated, when the memory is in the off-die check mode; the first burst length being less than the second burst length.
16 . The operation method according to claim 14 , wherein after the directly outputting the stored data and the first check code as second read data, the operation method further comprises: determining whether an extended function of the memory is enabled; and serializing the second read data and first extended data based on a third burst length, and then generating a plurality of third output data strings to be output through a plurality of data ports, if the memory is in the off-die check mode and the extended function is enabled; each of the third output data strings comprising a part of the stored data that is serially output, a part of the first check code, and a part of the first extended data.
17 . An operation method for a memory, the operation method comprising: determining a check mode of the memory in response to a mode selection signal; and parallelizing a first input data string of a first burst length received from each of data ports, and then generating first write data, when the mode selection signal indicates that the memory is in an on-die check mode; or parallelizing a second input data string of a second burst length received from each of data ports, and then generating second write data, when the mode selection signal indicates that the memory is in an off-die check mode; the second burst length being greater than the first burst length, the first write data comprising to-be-stored data, the second write data comprising the to-be-stored data and a corresponding second check code, the first input data string comprising a part of the to-be-stored data that is serially input, and the second input data string comprising a part of the to-be-stored data that is serially input and a part of the second check code.
18 . The operation method according to claim 17 , wherein the memory comprises a plurality of data storage blocks and a check code storage block, and the operation method further comprises: encoding the to-be-stored data in the received first write data to generate a corresponding third check code, and respectively storing the to-be-stored data and the third check code in the plurality of data storage blocks and the check code storage block, when the memory is in the on-die check mode; or respectively storing the to-be-stored data in the received second write data and the second check code in the plurality of data storage blocks and the check code storage block, when the memory is in the off-die check mode.
19 . The operation method according to claim 17 , wherein when the mode selection signal indicates that the memory is in the off-die check mode, the operation method further comprises: determining whether an extended function of the memory is enabled; and parallelizing a third input data string of a third burst length received from each of the data ports, and then generating third write data, if the memory is in the off-die check mode and the extended function is enabled; the third write data comprising the to-be-stored data, the corresponding second check code, and second extended data, and the third input data string comprising a part of the to-be-stored data that is serially input, a part of the second check code, and a part of the second extended data.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation application of International Application No. PCT/CN2025/116873 filed on August 26, 2025, which claims priority to Chinese Patent Application No.202411455538.1 filed on October 18, 2024. The disclosures of the above-referenced applications are hereby incorporated by reference in their entirety. TECHNICAL FIELD Embodiments of the present disclosure relate to the field of semiconductor technologies, and in particular, to a memory, a storage device, and a memory operation method. BACKGROUND With rapid development of computer technologies, requirements for a capacity and a speed of a memory are constantly increased. However, as the memory capacity increases, the possibility of a data error also increases. To improve reliability of data processing, an ECC (error checking and correction) check technology is widely applied to a dynamic random access memory (Dynamic Random Access Memory, DRAM). The ECC check is performed to check and correct a specific quantity of errors by encoding data, thereby reducing a failure rate of a storage system. However, at present, implementation of a mainstream ECC check scheme in a storage device on the market requires support from an additional hardware circuit and algorithm, increasing costs for producing a DRAM storage device. SUMMARY Embodiments of the present disclosure provide a memory, a storage device, and a memory operation method. According to a first aspect, an embodiment of the present disclosure provides a memory. The memory includes: multiple data storage blocks and a check code storage block; and a data check circuit, configured to: respectively obtain stored data and a corresponding first check code from the multiple data storage blocks and the check code storage block, and determine, in response to a received mode selection signal, whether to perform a data check operation. The data check circuit is further configured to: perform data check on the stored data based on the first check code, and output the stored data obtained after the data check as first read data, when the mode selection signal indicates that the memory is in an on-die check mode; or directly output the stored data and the first check code as second read data when the mode selection signal indicates that the memory is in an off-die check mode. The first check code in the second read data is employed by an external memory controller to perform a data check operation on the stored data. In some embodiments, the memory further includes an input/output circuit, configured to: receive the mode selection signal, and serialize the received first read data based on a first burst length and then generate multiple first output data strings to be output to multiple data ports, when the mode selection signal indicates that the memory is in the on-die check mode; or serialize the received second read data based on a second burst length and then generate multiple second output data strings to be output to the multiple data ports, when the mode selection signal indicates that the memory is in the off-die check mode. The first burst length is less than the second burst length. In some embodiments, each of the first output data strings includes a part of the stored data that is serially output, and each of the second output data strings includes a part of the stored data that is serially output and a part of the first check code. In some embodiments, the input/output circuit is further configured to: receive an extended function indication signal, and serialize the received second read data and first extended data based on a third burst length and then generate multiple third output data strings to be output to the multiple data ports, when the mode selection signal indicates that the memory is in the off-die check mode and the extended function indication signal indicates that the memory enables an extended function. Each of the third output data strings includes a part of the stored data that is serially output, a part of the first check code, and a part of the first extended data. In some embodiments, the input/output circuit is further configured to: parallelize a first input data string of a first burst length received from each of the data ports and then generate first write data to be output to the data check circuit, when the mode selection signal indicates that the memory is in the on-die check mode; or parallelize a second input data string of a second burst length received from each of the data ports and then generate second write data to be output to the data check circuit, when the mode selection signal indicates that the memory is in the off-die check mode. The first write data includes to-be-stored data, the second write data includes the to-be-stored data and a corresponding second check code, the first input data string includes a part of the to-be-stored data that is serially input, and the second input data string includes a part of the