US-20260128114-A1 - MEMORY DEVICE WITH BUILT-IN SELF-TEST

US20260128114A1US 20260128114 A1US20260128114 A1US 20260128114A1US-20260128114-A1

Abstract

The present application discloses a memory device. The memory device includes a one-time programmable (OTP) cell array, a physical unclonable function (PUF) cell array, and a controller. The OTP cell array includes a plurality of OTP cells. The PUF cell array includes a plurality of PUF cells. The controller performs a first read operation upon the PUF cell array to read a plurality of first bit values, performs a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, performs a comparison operation upon the first bit values and the second bit values, and determines whether to allow an OTP load operation for reading the OTP cell array according to a result of the comparison operation.

Inventors

Chi-Yi Shao
Chia-Cho Wu

Assignees

PUFsecurity Corporation

Dates

Publication Date: 20260507
Application Date: 20251103

Claims (20)

1 . A memory device comprising: a one-time programmable (OTP) cell array comprising a plurality of OTP cells; a physical unclonable function (PUF) cell array comprising a plurality of PUF cells; and a controller configured to perform a first read operation upon the PUF cell array to read a plurality of first bit values, perform a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, perform a comparison operation upon the plurality of first bit values and the plurality of second bit values, and determine whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation.
2 . The memory device of claim 1 , wherein: each two of the plurality of PUF cells are configured to be paired and have complementary bit values according to their physical characteristics; and the plurality of first bit values comprise bit values of a plurality of first PUF cells of the plurality of PUF cells and the plurality of second bit values comprise bit values of a plurality of second PUF cells of the plurality of PUF cells that are paired with the plurality of first PUF cells.
3 . The memory device of claim 2 , wherein the controller determines to allow the OTP load operation when the result of the comparison operation indicates that each first PUF cell of the plurality of first PUF cells has a bit value different from a bit value of a second PUF cell of the plurality of second PUF cells paired with the first PUF cell.
4 . The memory device of claim 2 , wherein: the controller determines to perform a failure handling operation when the result of the comparison operation indicates that a first PUF cell of the plurality of first PUF cells has a bit value same as a bit value of a second PUF cell of the plurality of second PUF cells paired with the first PUF cell, wherein the failure handling operation comprises at least one of sending an alarm and forbidding the OTP load operation.
5 . The memory device of claim 2 , wherein the controller determines to perform an enrollment operation upon the plurality of PUF cells when the result of the comparison operation indicates that the plurality of first bit values and the plurality of second bit values are all the same.
6 . The memory device of claim 1 , wherein: the first read operation is performed to read the plurality of first bit values from at least part of the plurality of PUF cells and the second read operation is performed to read the plurality of second bit values from the at least part of the plurality of PUF cells again.
7 . The memory device of claim 6 , wherein bit values of the plurality of PUF cells are independent of each other.
8 . The memory device of claim 6 , wherein: the plurality of PUF cells comprise a plurality of first PUF cells and a plurality of second PUF cells, and each of the plurality of first PUF cells is paired with a second PUF cell of the plurality of second PUF cells to have complementary bit values; and the first read operation and the second read operation are performed upon the plurality of first PUF cells.
9 . The memory device of claim 6 , wherein: the controller determines to perform a failure handling operation when the result of the comparison operation indicates that the plurality of first bit values read by the first read operation are different from the plurality of second bit values read by the second read operation; and the failure handling operation comprises at least one of sending an alarm and forbidding the OTP load operation.
10 . The memory device of claim 6 , wherein when the result of the comparison operation indicates that the plurality of first bit values read by the first read operation are same as the plurality of second bit values read by the second read operation, the controller is further configured to calculate a Hamming weight of the plurality of first bit values or the plurality of second bit values.
11 . The memory device of claim 10 , wherein the controller determines to allow the OTP load operation when the Hamming weight is within a predetermined range.
12 . The memory device of claim 11 , wherein the controller is further configured to perform an enrollment operation upon the plurality of PUF cells when the Hamming weight is 0% or 100%, and perform a failure handling operation when the Hamming weight is not 0%, 100% nor within the predetermined range, wherein the failure handling operation comprises at least one of sending an alarm and forbidding the OTP load operation.
13 . A method for confirming stability of a memory device, wherein the memory device comprises an one-time programmable (OTP) cell array, and a physical unclonable function (PUF) cell array, the OTP cell array comprises a plurality of OTP cells, the PUF cell array comprises a plurality of PUF cells, and the method comprises: performing a first read operation upon the PUF cell array to read a plurality of first bit values; performing a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation; performing a comparison operation upon the plurality of first bit values and the plurality of second bit values; and determining whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation.
14 . The method of claim 13 , wherein: each two of the plurality of PUF cells are configured to be paired and have complementary bit values according to their physical characteristics; and the plurality of first bit values comprise bit values of a plurality of first PUF cells of the plurality of PUF cells and the plurality of second bit values comprise bit values of a plurality of second PUF cells of the plurality of PUF cells that are paired with the plurality of first PUF cells.
15 . The method of claim 14 , wherein the step of determining whether to allow the OTP load operation for reading the OTP cell array at least according to the result of the comparison operation comprises: determining to allow the OTP load operation when the result of the comparison operation indicates that each first PUF cell of the plurality of first PUF cells has a bit value different from a bit value of a second PUF cell of the plurality of second PUF cells paired with the first PUF cell.
16 . The method of claim 14 , further comprising: determining to perform a failure handling operation when a first PUF cell of the plurality of first PUF cells has a bit value same as a bit value of a second PUF cell of the plurality of second PUF cells paired with the first PUF cell; wherein the failure handling operation comprises at least one of sending an alarm and forbidding the OTP load operation.
17 . The method of claim 14 , further comprising: determining to perform an enrollment operation upon the plurality of PUF cells when the result of the comparison operation indicates that the plurality of first bit values and the plurality of second bit values are all the same.
18 . The method of claim 13 , wherein: the first read operation is performed to read the plurality of first bit values from at least part of the plurality of PUF cells and the second read operation is performed to read the plurality of second bit values from the at least part of the plurality of PUF cells again.
19 . The method of claim 18 , further comprising: determining to perform a failure handling operation when the result of the comparison operation indicates that the plurality of first bit values read by the first read operation are different from the plurality of second bit values read by the second read operation; and wherein the failure handling operation comprises at least one of sending an alarm and forbidding the OTP load operation.
20 . The method of claim 18 , further comprising: calculating a Hamming weight of the plurality of first bit values or the plurality of second bit values when the result of the comparison operation indicates that the plurality of first bit values read by the first read operation are same as the plurality of second bit values read by the second read operation; and determining to allow the OTP load operation when the Hamming weight is within a predetermined range.

Description

CROSS REFERENCE This application claims the benefit of prior-filed U.S. provisional application No. 63/715,647, filed on November 4, 2024, which is incorporated by reference in its entirety. TECHNICAL FIELD The present disclosure relates to a memory device, and more particularly, to a memory device with a built-in self-test (BIST) function. DISCUSSION OF THE BACKGROUND Generally, when a system on chip (SoC) powers up, it follows a predefined boot sequence. For example, upon powering on, the SoC first performs basic hardware initialization. It then reads configuration data, such as security keys, boot configuration, and hardware settings, from the one-time programmable (OTP) memory for system setting and verification. Afterwards, the SoC may further proceed with CPU initialization, execute the bootloader from the read-only memory (ROM), and finally start the operating system (OS). However, during the initial stages of the SoC's boot process, the system voltages may not yet be stable. Such instability can lead to errors when reading data from the OTP memory. Since the data stored in the OTP memory may include critical content, such as system security keys and configuration data, the authentication and the boot process of the SoC may fail if the data are not correctly read from the OTP memory. Therefore, how to ensure the stability of OTP memory before reading data from it has become an issue to be solved. SUMMARY One aspect of the present disclosure provides a memory device. The memory device includes a one-time programmable (OTP) cell array, a physical unclonalbe function (PUF) cell array, and a controller. The OTP cell array includes a plurality of OTP cells. The PUF cell array includes a plurality of PUF cells. The controller performs a first read operation upon the PUF cell array to read a plurality of first bit values, performs a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, performs a comparison operation upon the plurality of first bit values and the plurality of second bit values, and determines whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation. Another aspect of the present disclosure provides a method for confirming stability of a memory device. The memory device includes an OTP cell array, a PUF cell array, and a controller. The OTP cell array includes a plurality of OTP cells, and the PUF cell array includes a plurality of PUF cells. The method includes performing a first read operation upon the PUF cell array to read a plurality of first bit values, performing a second read operation upon the PUF cell array to read a plurality of second bit values after the first read operation, performing a comparison operation upon the plurality of first bit values and the plurality of second bit values, and determining whether to allow an OTP load operation for reading the OTP cell array at least according to a result of the comparison operation. BRIEF DESCRIPTION OF THE PLOTTINGS A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures. FIG. 1 shows a system on chip (SoC) according to one embodiment of the present disclosure. FIG. 2 shows a memory device according to one embodiment of the present disclosure. FIG. 3 shows the paired PUF cells according to one embodiment of the present disclosure. FIG. 4 shows a flow chart of a method for confirming the stability of the memory device according to one embodiment of the present disclosure. FIG. 5 shows a flow chart for performing a step for determining whether to allow an OTP load operation according to one embodiment of the present disclosure. FIG. 6 shows a memory device according to another embodiment of the present disclosure. FIG. 7 shows a flow chart for performing a step for determining whether to allow an OTP load operation according to another embodiment of the present disclosure. DETAILED DESCRIPTION FIG. 1 shows a system on chip (SoC) 10 according to one embodiment of the present disclosure. The SoC 10 is an integrated circuit that integrate various components of a computer or other electronic systems onto a single chip. For example, the SoC 10 may include a central process unit (CPU) 11, an On-chip random access memory (RAM) 12, a direct memory access (DMA) controller 13, an arbiter 14, and a decoder 15. The CPU 11 is the main processing unit of the SoC 10 that executes instructions and performs calculations. The on-chop RAM 12 is a memory integrated into the SoC 10, used for temporary data storage and quick access by the CPU 11. The DMA controller 13 manages the direct transfer of data between memory and peripherals without involving the CPU 11 so as to increase the data transfer efficiency and reduce the burden