US-20260128116-A1 - INTERPOSERS FOR MEMORY DEVICE TESTING AND CHARACTERIZATION, INCLUDING INTERPOSERS FOR TESTING AND CHARACTERIZING DECISION FEEDBACK EQUALIZATION CIRCUITRY OF DDR5 MEMORY DEVICES

Abstract

Interposers for use in testing and characterizing memory devices, such as memory devices including decision feedback equalization circuitry, are disclosed herein. In one embodiment, an apparatus includes an interposer having a first interface couplable to a memory device, a second interface couplable to one or more testers, and a channel circuit between the first interface and the second interface. The channel circuit is configurable, via one or more resistive elements, to change a measurable value of a signal transmitted between the first interface and the second interface via the channel circuit.

Inventors

• Eric J. Stave
• Luis Nathan Perez Acosta
• Bryce A. Gardiner

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260507

Application Date

20251229

Claims (20)

1. 1 . A method of testing a device under test (DUT), the method comprising: providing an interposer having a first interface, a second interface couplable to a tester, and a channel circuit coupling the first interface to the second interface, wherein the channel circuit includes a plurality of electrical contacts configured to receive one or more circuit components to selectively enable corresponding circuit options of the channel circuit; operably connecting the DUT to the first interface of the interposer; and testing the DUT by transmitting a signal to or from the DUT via the channel circuit of the interposer.
2. 2 . The method of claim 1 , further comprising operably connecting the second interface of the interposer to a tester, wherein testing the DUT by transmitting the signal includes transmitting the signal between the DUT and the tester via the first interface, the channel circuit, and the second interface.
3. 3 . The method of claim 2 , wherein operably connecting the second interface of the interposer to the tester comprises operably connecting the second interface to a motherboard via a socket, wherein the motherboard is operably connected to the tester.
4. 4 . The method of claim 1 , wherein the DUT includes a memory device having decision feedback equalization (DFE) circuitry, and wherein testing the DUT comprises characterizing the DFE circuitry by monitoring an ability of the DFE circuitry to mitigate an effect of inter-symbol interference (ISI) on the signal transmitted to the DUT via the channel circuit.
5. 5 . The method of claim 1 , further comprising operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts.
6. 6 . The method of claim 5 , wherein operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts includes enabling at least one of the corresponding circuit options that includes a stub configured to generate reflections on the channel circuit.
7. 7 . The method of claim 5 , wherein operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts includes enabling at least one of the corresponding circuit options that includes a simulated on-die termination value of another device.
8. 8 . The method of claim 5 , wherein operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts includes enabling at least one of the corresponding circuit operations that includes a simulated input/output capacitance value of another device.
9. 9 . The method of claim 5 , wherein the plurality of electrical contacts are arranged in one or more pairs, wherein each pair is configured to receive a circuit component to complete an electrical connection across corresponding electrical contacts of the pair, and wherein operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts includes operably connecting at least one of the one or more circuit components to both electrical contacts of a pair of the one or more pairs and thereby enabling at least one of the corresponding circuit options of the channel circuit.
10. 10 . The method of claim 5 , wherein operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts includes operably connecting a resistor, a capacitor, a zero-ohm resistor, and/or a jumper to at least one of the plurality of electrical contacts.
11. 11 . The method of claim 1 , wherein: the channel circuit includes— a first arrangement of electrical contacts corresponding to a one-device-per-channel configuration, and a second arrangement of electrical contacts corresponding to a two-device-per-channel configuration; and the method further comprises operably connecting at least one of the one or more circuit components to at least one of the plurality of electrical contacts such that either the one-device-per-channel configuration or the two-device-per-channel configuration is enabled.
12. 12 . The method of claim 1 , wherein operably connecting the DUT to the first interface of the interposer comprises reversibly connecting the DUT to a socket of the first interface.
13. 13 . The method of claim 1 , further comprising: disconnecting the DUT from the first interface of the interposer after testing the DUT; and operably connecting a second DUT to the first interface of the interposer for testing.
14. 14 . A method of characterizing decision feedback equalization (DFE) circuitry of a memory device, the method comprising: providing an interposer having a channel circuit configurable to generate inter-symbol interference (ISI) on signals transmitted over the channel circuit; operably connecting the memory device to a first interface of the interposer; transmitting a signal to the memory device via the channel circuit; and monitoring an ability of the DFE circuitry of the memory device to mitigate effects of ISI on the signal transmitted via the channel circuit.
15. 15 . The method of claim 14 , wherein: the channel circuit includes a plurality of electrical contacts arranged in one or more pairs, each pair configured to receive one or more circuit components to complete an electrical connection across corresponding electrical contacts of the pair; and the method further comprises operably connecting a circuit component to electrical contacts of a pair of the one or more pairs such that a corresponding circuit option of the channel circuit is enabled.
16. 16 . The method of claim 15 , wherein the corresponding circuit option includes a stub configured to generate reflections on the channel circuit.
17. 17 . The method of claim 15 , wherein the corresponding circuit option includes a circuit option configured to simulate an on-die termination value of another memory device.
18. 18 . The method of claim 15 , wherein the corresponding circuit option includes a circuit option configured to simulate an input/output capacitance value of another memory device.
19. 19 . A method of testing a memory device, the method comprising: providing an interposer including a channel circuit having a plurality of pairs of electrical contacts, wherein each pair of electrical contacts is configured to receive a circuit component to complete an electrical connection across corresponding electrical contacts of the pair and thereby enable a corresponding circuit option of the channel circuit; selectively enabling at least one circuit option of the channel circuit by electrically coupling electrical contacts of at least one of the plurality of pairs of electrical contacts to one another via a circuit component; operably connecting the memory device to the interposer; and testing the memory device, wherein testing the memory device includes transmitting a signal to or from the memory device via the channel circuit.
20. 20 . The method of claim 19 , wherein the memory device includes decision feedback equalization (DFE) circuitry, and wherein transmitting the signal to or from the memory device via the channel circuit comprises generating inter-symbol interference (ISI) on the signal to characterize an ability of the DFE circuitry to mitigate effects of the ISI.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application is a continuation of U.S. application Ser. No. 18/109,830, filed Feb. 14, 2023, now U.S. Pat. No. 12,512,179, which claims priority to U.S. Provisional Patent Application No. 63/347,483, filed May 31, 2022, the disclosures of which are incorporated herein by reference in their entireties. TECHNICAL FIELD The present disclosure is related to interposers for use in testing and characterizing memory devices, and associated systems, devices, and methods. For example, some embodiments of the present technology are directed to interposers for use in testing or characterizing decision feedback equalization (DFE) circuitry of memory devices, such as of double data rate fifth generation (DDR5) memory devices. BACKGROUND Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including static random-access memory (SRAM), dynamic random-access memory (DRAM), and synchronous dynamic random-access memory (SDRAM), among others, may require a source of applied power to maintain its data. Non-volatile memory, by contrast, can retain its stored data even when not externally powered. Non-volatile memory is available in a wide variety of technologies, including flash memory (e.g., NAND and NOR) phase change memory (PCM), ferroelectric random-access memory (FeRAM), resistive random-access memory (RRAM), and magnetic random-access memory (MRAM), among others. Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present disclosure. The drawings should not be taken to limit the disclosure to the specific embodiments depicted, but are for explanation and understanding only. FIG. 1 is a partially schematic representation of a memory testing system configured in accordance with various embodiments of the present technology. FIG. 2A is a partially schematic side view of an interposer configured in accordance with various embodiments of the present technology. FIG. 2B is a partially schematic top view of the interposer of FIG. 2A. FIG. 2C is a partially schematic bottom view of the interposer of FIGS. 2A and 2B. FIG. 3 is a partially schematic circuit diagram of a channel circuit included on an interposer configured in accordance with various embodiments of the present technology. FIGS. 4A and 4B are eye plots corresponding to a two-device-per-channel implementation of the circuit diagram of FIG. 3. FIGS. 5A and 5B are eye plots corresponding to a one-device-per-channel implementation of the circuit diagram of FIG. 3. FIG. 6 is a partially schematic partial top view of another interposer configured in accordance with various embodiments of the present technology. FIG. 7 is a flow diagram illustrating a method of testing or characterizing a memory device in accordance with various embodiments of the present technology. DETAILED DESCRIPTION The technology disclosed herein relates to interposers for use in testing and characterizing memory devices, and associated systems, devices, and methods. In the illustrated embodiments below, interposers of the present technology are primarily described in the context of testing or characterizing DFE circuitry of DDR5 DRAM memory devices. Interposers configured in accordance with various embodiments of the present technology, however, can be used to test or characterize circuitry other than DFE circuitry on DDR5 DRAM memory devices, including circuitry on other types of memory devices and systems (e.g., DDR, DDR2, DDR3, DDR4) and/or on memory devices and systems incorporating other types of storage media (e.g., PCM, SRAM, FRAM, RRAM, MRAM, read only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and/or non-volatile, flash (e.g., NAND and/or NOR) storage media). Additionally, or alternatively, interposers of the present technology can be used to test devices or systems other than memory devices, such as memory controllers, central processor units, or serializer-deserializer (SERDES) links (e.g., SERDES controllers). A person skilled in the art will understand that the technology