US-20260128232-A1 - CAPACITOR ARRAY

US20260128232A1US 20260128232 A1US20260128232 A1US 20260128232A1US-20260128232-A1

Abstract

A capacitor array includes a first bottom plate, at least one top plate, at least one strip-shaped bottom plate, a first via, a second bottom plate, and a second via. The at least one top plate is disposed above the first bottom plate. The at least one strip-shaped bottom plate is disposed above the first bottom plate, and disposed outside the at least one top plate. The first via connects the first bottom plate to the at least one strip-shaped bottom plate. The second bottom plate is disposed above the at least one top plate and the at least one strip-shaped bottom plate. The second via connects the at least one bottom plate to the second bottom plate.

Inventors

Min-Yuan Wu
Yan-Ting WU

Assignees

REALTEK SEMICONDUCTOR CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251031
Priority Date: 20241106

Claims (10)

1 . A capacitor array, comprising: a first bottom plate; at least one top plate, disposed above the first bottom plate; at least one strip-shaped bottom plate, disposed above the first bottom plate, and disposed outside the at least one top plate; a first via, connected the first bottom plate to the at least one strip-shaped bottom plate; a second bottom plate, disposed above the at least one top plate and the at least one strip-shaped bottom plate; and a second via, connected the at least one strip-shaped bottom plate to the second bottom plate.
2 . The capacitor array of claim 1 , wherein the at least one top plate comprises: a first top plate, disposed above the first bottom plate; and a second top plate, disposed above the first top plate.
3 . The capacitor array of claim 2 , wherein the at least one strip-shaped bottom plate comprises: a first strip-shaped bottom plate, disposed above the first bottom plate, and disposed around the first top plate; and a second strip-shaped bottom plate, disposed above the first strip-shaped bottom plate, and disposed around the second top plate.
4 . The capacitor array of claim 3 , further comprising: a third via, connected the first top plate to the second top plate; and a fourth via, connected the first strip-shaped bottom plate to the second strip-shaped bottom plate.
5 . The capacitor array of claim 4 , wherein the at least one top plate further comprises: a third top plate, disposed above the second top plate; wherein the at least one strip-shaped bottom plate further comprises: a third strip-shaped bottom plate, disposed above the second strip-shaped bottom plate, and disposed around the third top plate.
6 . The capacitor array of claim 5 , further comprising: a fifth via, connected the second top plate to the third top plate; and a sixth via, connected the second strip-shaped bottom plate to the third strip-shaped bottom plate.
7 . The capacitor array of claim 1 , further comprising: at least one ground plate, disposed outside the at least one top plate and the at least one strip-shaped bottom plate.
8 . The capacitor array of claim 7 , wherein the at least one ground plate comprises: a first ground plate, disposed around the first bottom plate; a second ground plate, disposed above the first ground plate, and disposed around the at least one top plate and the at least one strip-shaped bottom plate; and a third ground plate, disposed above the second ground plate, and disposed around the second bottom plate.
9 . The capacitor array of claim 1 , wherein the at least one strip-shaped bottom plate comprises: a first strip-shaped sub-bottom plate, disposed on a first side of the at least one top plate; and a second strip-shaped sub-bottom plate, disposed on a second side of the at least one top plate, wherein the first side is opposite to the second side.
10 . The capacitor array of claim 9 , further comprising: a first sub-ground plate, disposed outside the first strip-shaped sub-bottom plate; and a second sub-ground plate, disposed outside the second strip-shaped sub-bottom plate.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present disclosure relates to a capacitor array, especially to a capacitor array capable of reducing the influence of noise. 2. Description of Related Art A capacitor array can be applied in an analog to digital converter (ADC). The capacitor array includes a top plate and a bottom plate. In the industry, the top plate is typically placed on the outer side, and the bottom plate is placed on the inner side. However, the top plate is more sensitive. If the top plate is placed on the outer side, the capacitor array will be easily affected by noise. SUMMARY OF THE INVENTION In some aspects, an object of the present disclosure is to, but not limited to, provides a capacitor array that makes an improvement to the prior art. An embodiment of the capacitor array of the present disclosure includes a first bottom plate, at least one top plate, at least one strip-shaped bottom plate, a first via, a second bottom plate, and a second via. The at least one top plate is disposed above the first bottom plate. The at least one strip-shaped bottom plate is disposed above the first bottom plate, and disposed outside the at least one top plate. The first via connects the first bottom plate to the at least one strip-shaped bottom plate. The second bottom plate is disposed above the at least one top plate and the at least one strip-shaped bottom plate. The second via connects the at least one bottom plate to the second bottom plate. Technical features of some embodiments of the present disclosure make an improvement to the prior art. In the capacitor array of the present disclosure, the top plate is disposed on the inner side, thereby reducing the influence of noise on the top plate. Specifically, the top plate of the capacitor array of the present disclosure is surrounded by the bottom plate in the X-axis, Y-axis, and Z-axis directions. Therefore, the top plate of the capacitor array of the present disclosure is not only interference-resistant in the X-axis and Y-axis directions, but also additionally interference-resistant in the Z-axis direction, thereby achieving an improved three-dimensional interference-resistant capability. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows an embodiment of a comparator and a capacitor array of an analog to digital conversion circuit of the present disclosure. FIG. 2 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 3 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 4 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 5 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 6 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 7 shows an embodiment of a partial structure of a capacitor array of the present disclosure. FIG. 8 shows an embodiment of a cross-sectional view of a capacitor array of the present disclosure. FIG. 9 shows an embodiment of a cross-sectional view of a capacitor array of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS To address the issue in the prior art in which the top plate of the capacitor array is easily affected by noise, the present disclosure provides a capacitor array, which will be described in detail as shown below. FIG. 1 shows an embodiment of a comparator Cmp and a capacitor array 100 of an analog to digital conversion circuit 1000 of the present disclosure. As shown in the figure, a node between the inverting input terminal of the comparator Cmp and one terminal of the capacitor array 100 is defined as a top plate node Ct, and the other terminal of the capacitor array 100 is defined as a bottom plate node Cb. FIGS. 2 to 7 show embodiments of partial structures of the capacitor array 100 of the present disclosure. As shown in the figure, unit U1 is a unit of the capacitor array 100, and the unit U1 represents a top view of the capacitor array 100. In addition, the unit U2 is another unit of the capacitor array 100, and the unit U2 represents a bottom view of the capacitor array 100. FIGS. 2 to 7 illustrate the overall structure of the present disclosure in detail by means of the top view unit U1 and the bottom view unit U2 of the capacitor array 100. Please refer to FIG. 2. The capacitor array 100 includes a connection plate 111, ground plates 121, 122, a connection plate 123, and a via 124. The connection plate 111 is connected to the bottom plate node Cb in FIG. 1. The ground plates 121, 122 and the connection plate 123 are disposed above the connection plate 111, and the ground plates 121, 122 are disp