US-20260128252-A1 - VERTICAL ELECTRODE CONFIGURATION

Abstract

Embodiments disclosed herein include electrode configurations for a plasma-enhanced deposition process. In an example, an electrode configuration includes a stack of wafer processing regions aligned along a vertical axis. A plurality of electrodes is surrounding the stack of wafer processing regions. Each one of the plurality of electrodes is extending along the vertical axis.

Inventors

• Kallol Bera
• Rupali Sahu
• Sathya Swaroop GANTA
• Shahid Rauf

Assignees

• APPLIED MATERIALS, INC.

Dates

Publication Date

20260507

Application Date

20241107

Claims (20)

1. 1 . An electrode configuration for a plasma-enhanced deposition process comprising: a stack of wafer processing regions aligned along a vertical axis; and a plurality of electrodes surrounding the stack of wafer processing regions, each one of the plurality of electrodes extending along the vertical axis.
2. 2 . The plasma source of claim 1 , wherein each of the plurality of electrodes has the same RF potential amplitude.
3. 3 . The plasma source of claim 2 , wherein each one of the plurality of electrodes have phase difference of 30-150 degrees with respect to an adjacent one of the plurality of electrodes.
4. 4 . The plasma source of claim 1 , wherein the plurality of electrodes has a non-sinusoidal electrode potential.
5. 5 . The plasma source of claim 4 , wherein each one of the plurality of electrodes is time delayed with respect to an adjacent one of the plurality of electrodes.
6. 6 . The plasma source of claim 1 , wherein the plurality of electrodes comprises at least three electrodes, each shaped to have curvature in the wafer plane.
7. 7 . The plasma source of claim 1 , wherein the plurality of electrodes comprises at least four electrodes.
8. 8 . The plasma source of claim 7 , wherein the plurality of electrodes comprises five, or more electrodes.
9. 9 . A plasma process chamber, comprising: a stack of wafer support pedestals aligned along a vertical axis, each of the wafer support pedestals comprising a corresponding processing region; and a plurality of electrodes surrounding the stack of wafer processing regions, each one of the plurality of electrodes extending along the vertical axis.
10. 10 . The plasma process chamber of claim 9 , wherein each of the plurality of electrodes has the same RF potential amplitude.
11. 11 . The plasma process chamber of claim 10 , wherein each one of the plurality of electrodes has phase difference of 30-150 degrees with respect to an adjacent one of the plurality of electrodes.
12. 12 . The plasma process chamber of claim 10 , wherein each one of the plurality of electrodes is time delayed with respect to an adjacent one of the plurality of electrodes.
13. 13 . The plasma process chamber of claim 9 , wherein the plurality of electrodes has a non-sinusoidal electrode potential.
14. 14 . The plasma process chamber of claim 9 , wherein the plurality of electrodes comprises exactly three electrodes.
15. 15 . The plasma process chamber of claim 9 , wherein the plurality of electrodes comprises at least four electrodes.
16. 16 . The plasma process chamber of claim 15 , wherein the plurality of electrodes comprises five electrodes, six electrodes or more electrodes.
17. 17 . A process chamber, comprising: a plurality of vertically stacked ceramic wafer pedestals; and a plurality of RF electrodes, wherein each one of the plurality of RF electrodes carries the same RF potential amplitude but has phase difference with an adjacent one of the plurality of electrodes of 30-150 degrees.
18. 18 . The process chamber of claim 17 , wherein the number of electrodes and phase-difference between the adjacent electrodes is adjusted so that diametrically opposite electrodes have about 180 degrees phase difference.
19. 19 . The process chamber of claim 17 , wherein the plurality of electrodes comprises at least three electrodes.
20. 20 . The process chamber of claim 19 , wherein each one of the plurality of RF electrodes has a phase difference with an adjacent one of the plurality of electrodes of 30-150 degrees.

Description

FIELD Embodiments of the present disclosure pertain to the field of semiconductor processing and, in particular, vertical electrode configurations. DESCRIPTION OF RELATED ART Deposition of films on a substrate is an important process in a variety of industries including semiconductor processing, diffusion barrier coatings, and dielectrics. In the semiconductor industry, in particular, miniaturization requires atomic level control of film deposition to produce conformal coatings on high aspect structures. One method for deposition of films with control and conformal deposition is atomic layer deposition (ALD), which employs sequential surface reactions to form layers of a same precise thickness on all parts of a structure. Most ALD processes are based on binary reaction sequences which deposit a binary compound film. Because the surface reactions are sequential, the two gas phase reactants are not in contact, and possible gas phase reactions that may form and deposit particles are limited. SUMMARY Embodiments disclosed herein include electrode configurations for a plasma-enhanced deposition process. The electrode configuration includes a stack of wafer processing regions aligned along a vertical axis. A plurality of electrodes is surrounding the stack of wafer processing regions. Each one of the plurality of electrodes is extending along the vertical axis. Embodiments disclosed herein include a plasma process chamber including a stack of wafer support pedestals aligned along a vertical axis, each of the wafer support pedestals including a corresponding processing region. A plurality of electrodes is surrounding the stack of wafer processing regions, each one of the plurality of electrodes extending along the vertical axis. Embodiments disclosed herein include a process chamber including a plurality of vertically stacked ceramic wafer pedestals with corresponding wafer processing regions. The process chamber also includes a plurality of RF electrodes. Each one of the plurality of RF electrodes carries the same potential but is out of phase with an adjacent one of the plurality of electrodes by 45-135 degrees. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is an angled view of a vertical electrode configuration for batch processing, in accordance with an embodiment of the present disclosure. FIG. 1B is a plan view and associated schematic of a vertical electrode configuration for batch processing, and FIG. 1C is an associated cross-sectional view, in accordance with an embodiment of the present disclosure. FIG. 1D illustrates non-sinusoidal electrode potentials, in accordance with an embodiment of the present disclosure. FIGS. 1E and 1F illustrate a top-down view of a chamber and a computational setup, respectively, in accordance with an embodiment of the present disclosure. FIG. 2 is a schematic of a vertical electrode configuration and associated match circuit, in accordance with an embodiment of the present disclosure. FIGS. 3A and 3B illustrate top-down views of batch processing chambers with vertical electrodes, in accordance with an embodiment of the present disclosure. FIGS. 3C and 3D illustrate top-down views of batch processing chambers with vertical electrodes, in accordance with another embodiment of the present disclosure. FIG. 4 illustrates a schematic top-view diagram of an example multi-chamber processing system according to one or more embodiments of the disclosure. FIG. 5 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed according to an embodiment. DETAILED DESCRIPTION The disclosed embodiments relate to vertical electrode configurations. In the following description, numerous specific details are set forth, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. Most film properties cannot meet practical requirements due to lack of continuity, lack of conformality, poor film thickness control, and poor film composition control, such as hydrogen contamination and/or different bonding states of carbon in the film. Traditionally, films formed by chemical vapor deposition (CVD) and physical vapor deposition (PVD) processes are often non-continuous and not conformal. Additionally, the CVD process generally has less thickness control than an ALD process. Thermal atomic layer deposition (ALD) methods typically prov