US-20260128261-A1 - PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

Abstract

A decrease of an etching rate of a substrate can be suppressed, and energy of ions irradiated to an inner wall of a chamber main body can be reduced. A plasma processing apparatus includes a DC power supply configured to generate a negative DC voltage to be applied to a lower electrode of a stage. In a plasma processing performed by using the plasma processing apparatus, a radio frequency power is supplied to generate plasma by exciting a gas within a chamber. Further, the negative DC voltage from the DC power supply is periodically applied to the lower electrode to attract ions in the plasma onto the substrate placed on the stage. A ratio occupied, within each of cycles, by a period during which the DC voltage is applied to the lower electrode is set to be equal to or less than 40%.

Inventors

• Koichi Nagami
• Kazunobu Fujiwara
• Tatsuro Ohshita
• Takashi Dokan
• Koji Maruyama
• Kazuya Nagaseki
• Shinji Himori

Assignees

• TOKYO ELECTRON LIMITED

Dates

Publication Date

20260507

Application Date

20251229

Priority Date

20170818

Claims (20)

1. 1 . A plasma processing apparatus, comprising: a chamber; a stage disposed in the chamber and having a substrate-holding electrode and a bias electrode different from the substrate-holding electrode; an RF power source configured to supply an RF power and to excite a gas supplied into the chamber; a DC voltage source configured to supply a DC voltage to at least one of the substrate-holding electrode and the bias electrode; a switch connected between the DC voltage source and the bias electrode and configured to selectively connect and disconnect the DC voltage source and the bias electrode; and controller circuitry configured to control the RF power source and the switch to alternately repeat: a first period, in which the RF power is applied while the DC voltage is not applied to the bias electrode; and a second period, in which the DC voltage is applied to the bias electrode while the RF power is not applied.
2. 2 - 17 . (canceled)
3. 18 . The plasma processing apparatus of claim 1 , wherein the controller circuitry controls the switch such that the DC voltage is periodically applied to the bias electrode with a duty ratio of 40% or less.
4. 19 . The plasma processing apparatus of claim 18 , wherein the DC voltage is a negative DC voltage.
5. 20 . The plasma processing apparatus of claim 19 , wherein the duty ratio is equal to or less than 35%.
6. 21 . The plasma processing apparatus of claim 20 , wherein the duty ratio is equal to or less than 25%.
7. 22 . The plasma processing apparatus of claim 18 , wherein the switch includes at least one field effect transistor.
8. 23 . The plasma processing apparatus of claim 22 , wherein the at least one field effect transistor includes a first field effect transistor and a second field effect transistor having a channel polarity different from the first field effect transistor.
9. 24 . The plasma processing apparatus of claim 23 , wherein a source of the first field effect transistor is connected to the DC voltage source; a source of the second field effect transistor is connected to ground; a gate of the first field effect transistor is connected to a gate of the second field effect transistor; the controller circuitry is connected to a node between the gate of the first field effect transistor and the gate of the second field effect transistor; a drain of the first field effect transistor is connected to a drain of the second field effect transistor; and the bias electrode is connected to a node between the drain of the first field effect transistor and the drain of the second field effect transistor.
10. 25 . The plasma processing apparatus of claim 24 , wherein an RF filter is disposed between the switch and the bias electrode.
11. 26 . The plasma processing apparatus of claim 25 , wherein: the switch includes a resistor element electrically connected to the drain of the first field effect transistor and the drain of the second field effect transistor; and the RF filter is disposed between the resistor element and the bias electrode.
12. 27 . The plasma processing apparatus of claim 19 , wherein the switch includes at least one field effect transistor.
13. 28 . The plasma processing apparatus of claim 27 , wherein the at least one field effect transistor includes a first field effect transistor and a second field effect transistor having a channel polarity different from the first field effect transistor.
14. 29 . The plasma processing apparatus of claim 28 , wherein a source of the first field effect transistor is connected to the DC voltage source; a source of the second field effect transistor is connected to ground; a gate of the first field effect transistor is connected to a gate of the second field effect transistor; the controller circuitry is connected to a node between the gate of the first field effect transistor and the gate of the second field effect transistor; a drain of the first field effect transistor is connected to a drain of the second field effect transistor; and the bias electrode is connected to a node between the drain of the first field effect transistor and the drain of the second field effect transistor.
15. 30 . The plasma processing apparatus of claim 29 , wherein an RF filter is disposed between the switch and the bias electrode.
16. 31 . The plasma processing apparatus of claim 30 , wherein: the switch includes a resistor element electrically connected to the drain of the first field effect transistor and the drain of the second field effect transistor; and the RF filter is disposed between the resistor element and the bias electrode.
17. 32 . The plasma processing apparatus of claim 1 , further comprising: a plurality of DC voltage sources including the DC voltage source; and a plurality of switches including the switch, wherein the controller circuitry is configured to control the plurality of switches such that DC voltages from the plurality of DC voltage sources are applied to the bias electrode sequentially within each cycle.
18. 33 . The plasma processing apparatus of claim 1 , further comprising: a waveform adjuster disposed between the switch and the bias electrode, wherein the waveform adjuster is configured to adjust a waveform of the DC voltage to have a triangular shape.
19. 34 . A plasma processing apparatus, comprising: a chamber; a stage disposed in the chamber and having a substrate-holding electrode and a bias electrode different from the substrate-holding electrode; an RF power source configured to supply an RF power to excite a gas supplied into the chamber; a DC voltage source configured to supply a DC voltage to at least one of the substrate-holding electrode and the bias electrode; a switch connected between the DC voltage source and the bias electrode and configured to selectively connect and disconnect the DC voltage source and the bias electrode, the switch including: at least one field effect transistor; a capacitor; and a resistor element; and controller circuitry configured to control the RF power source and the switch to alternately repeat: a first period, in which the RF power is applied while the DC voltage is not applied to the bias electrode; and a second period, in which the DC voltage is applied to the bias electrode while the RF power is not applied.
20. 35 . The plasma processing apparatus of claim 34 , wherein the at least one field effect transistor includes a first field effect transistor and a second field effect transistor, a source of the first field effect transistor is connected to a cathode of the DC voltage source, a first end of the capacitor is connected to the cathode of the DC voltage source and the source of the first field effect transistor, and a second end of the capacitor is connected to a source of the second field effect transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation application of U.S. patent application Ser. No. 17/495,908, filed on Oct. 7, 2021, which is a continuation of U.S. patent application Ser. No. 16/722,248, filed on Dec. 20, 2019 (now U.S. Pat. No. 11,170,979), which is a continuation of U.S. patent application Ser. No. 16/104,512, filed on Aug. 17, 2018 (now U.S. Pat. No. 10,553,407), which claims the benefit of Japanese Patent Application No. 2017-157832 filed on Aug. 18, 2017, the entire disclosures of each are incorporated herein by reference. TECHNICAL FIELD The various aspects and embodiments described herein pertain generally to a plasma processing method and a plasma processing apparatus. BACKGROUND In the manufacture of an electronic device, a plasma processing apparatus is used. The plasma processing apparatus is generally equipped with a chamber main body, a stage and a radio frequency power supply. An internal space of the chamber main body is configured as a chamber. The chamber main body is grounded. The stage is provided within the chamber and configured to support a substrate placed thereon. The stage includes a lower electrode. The radio frequency power supply is configured to supply a radio frequency power to excite a gas within the chamber. In this plasma processing apparatus, ions are accelerated by a potential difference between a potential of the lower electrode and a potential of the plasma, and the accelerated ions are irradiated to the substrate. In the plasma processing apparatus, a potential difference is also generated between the chamber main body and the plasma. When the potential difference between the chamber main body and the plasma is large, energy of ions irradiated to an inner wall of the chamber main body is increased, so that particles are released from the chamber main body. The particles released from the chamber main body contaminates the substrate placed on the stage. To suppress the generation of these particles, Patent Document 1 discloses a technique using an adjustment mechanism configured to adjust a ground capacity of the chamber. The adjustment mechanism described in Patent Document 1 is configured to adjust an area ratio between a cathode and an anode facing the chamber, that is, an A/C ratio. Patent Document 1: Japanese Patent Laid-open Publication No. 2011-228694 SUMMARY As one kind of the plasma processing apparatus, there is used a plasma processing apparatus configured to supply a radio frequency power for bias (“radio frequency bias power”) to the lower electrode. The radio frequency bias power is supplied to the lower electrode to increase an etching rate of the substrate by increasing the energy of the ions irradiated to the substrate. In this plasma processing apparatus, if the potential of the plasma is increased, the potential difference between the plasma and the chamber main body is increased, and the energy of the ions irradiated to the inner wall of the chamber main body is also increased. In this regard, it is required to suppress a decrease of the etching rate of the substrate and reduce the energy of the ions irradiated to the inner wall of the chamber main body. In one exemplary embodiment, there is provided a plasma processing method performed in a plasma processing apparatus. The plasma processing apparatus includes a chamber main body, a stage, a radio frequency power supply and one or more DC power supplies. An internal space of the chamber main body is configured as a chamber. The stage is provided within the chamber main body. The stage includes a lower electrode. The stage is configured to support a substrate placed thereon. The radio frequency power supply is configured to supply a radio frequency power for exciting a gas supplied into the chamber. The one or more DC power supplies are configured to generate a negative DC voltage to be applied to the lower electrode. The plasma processing method includes (i) supplying the radio frequency power from the radio frequency power supply to generate plasma of the gas supplied into the chamber; and (ii) applying the negative DC voltage to the lower electrode from the one or more DC power supplies to attract ions in the plasma onto the substrate. In the applying of the DC voltage, the DC voltage is applied to the lower electrode periodically, and a ratio occupied, within each of cycles, by a period during which the DC voltage is applied to the lower electrode is set to be equal to or less than 40%. Dependency of an etching rate of the substrate upon the ratio occupied, within each cycle, by the period during which the negative DC voltage is applied to the lower electrode, that is, a duty ratio is small. Meanwhile, when the duty ratio is small, particularly, when the duty ratio is equal to or less than 40%, an etching rate of the chamber main body is greatly decreased. That is, energy of ions irradiated to an inner wall of the chamber main body is decreased. Thus, according to the