US-20260128660-A1 - ADAPTIVE POWER LIMITATION CIRCUIT AND HANDSHAKE DEACTIVATION/REACTIVATION PROTOCOL FOR A MULTIPHASE DCDC CONTROLLER

US20260128660A1US 20260128660 A1US20260128660 A1US 20260128660A1US-20260128660-A1

Abstract

A method pulls down, by a responder device having at least two responder channels, a first pin to a pre-determined voltage level when all responder channels of the responder device are turned OFF; detects that a requestor coupled to the responder has frozen a synchronization signal on a second pin when voltage on the first pin is below a certain threshold; terminates a pulling down, by the responder device, the first pin to the pre-determined voltage level after the responder device detects no activity on the second pin; generates a synchronization signal, by the requestor device, on a second pin when a load power demand reaches a reactivation threshold; and turns ON all responder channels of the responder device, by the responder device, when the responder device detects the synchronization signal on the second pin.

Inventors

Marco Cignoli
Andrea Smaniotto
Alessandro Bacceli

Assignees

ALLEGRO MICROSYSTEMS, LLC

Dates

Publication Date: 20260507
Application Date: 20241107

Claims (20)

1 . A method, comprising: (a) pulling down, by a responder device having at least two responder channels, a first pin to a pre-determined voltage level when a responder channel of the responder device is turned OFF; (b) detecting that a requestor device coupled to the responder device has frozen a synchronization signal on a second pin when voltage on the first pin is below a certain threshold; and (c) terminating a pulling down, by the responder device, of the first pin to the pre-determined voltage level after the responder device detects no activity on the second pin.
2 . The method according to claim 1 , further comprising: (d) turning OFF, by the responder device, a responder channel when a requested load power is below a deactivation threshold.
3 . The method according to claim 1 , further comprising: (d) turning OFF a synchronization signal, by the requestor device, on the second pin when voltage on the first pin is below a certain threshold.
4 . The method according to claim 1 , wherein said (a) pulling down, by the responder device, the first pin to a pre-determined voltage level when the responder channel of the responder device is turned OFF for a first predetermined period of time.
5 . The method according to claim 3 , wherein said (d) turning OFF the synchronization signal, by the requestor device, on second the second pin when voltage on the first pin is below a certain threshold for a second predetermined period of time.
6 . The method as claimed in claim 4 , wherein said (d) turning OFF, by the responder device, responder channels of the responder device, one by one in a pre-determined sequence at a pre-determined time interval, when a requested load power is below a deactivation threshold.
7 . The method according to claim 1 , wherein said (c) terminating the pulling down, by the responder device, of the first pin to the pre-determined voltage level after the responder device detects no activity on the second pin for a first predetermined period of time.
8 . The method according to claim 4 , wherein said (c) terminating the pulling down, by the responder device, of the first pin to the pre-determined voltage level after the responder device detects no activity on the second pin for a second predetermined period of time.
9 . The method according to claim 1 , wherein the first pin is a pin for sharing a compensation voltage and the second pin is a pin to synchronize other device operation with a clock signal.
10 . The method according to claim 1 , wherein the responder device is included in a multiphase boost converter controller.
11 . The method according to claim 1 , wherein the responder device is included in a multiphase buck converter controller.
12 . The method according to claim 1 , wherein said (a) pulling down, by a responder device having at least two responder channels, a first pin to a pre-determined voltage level when all responder channels of the responder device are turned OFF.
13 . The method according to claim 12 , further comprising: (d) turning OFF, by the responder device, all the responder channels of the responder device when a requested load power is below a deactivation threshold.
14 . The method as claimed in claim 13 , wherein said (d) turning OFF, by the responder device, the responder channels of the responder device, one by one in a pre-determined sequence at a pre-determined time interval, when a requested load power is below a deactivation threshold.
15 . The method according to claim 10 , wherein said (a) pulling down, by the responder device, the first pin to a pre-determined voltage level when all the responder channels of the responder device are turned OFF for a first predetermined period of time.
16 . A method, comprising: (a) detecting on a first pin, by a responder device, a synchronization signal generated by a requestor device, when a load power demand reaches a reactivation threshold; and (b) turning ON a responder channel, by the responder device, when the responder device detects the synchronization signal on the first pin.
17 . The method according to claim 16 , wherein the requestor device generates the synchronization signal on a first pin when the load power demand reaches the reactivation threshold after a first predetermined period of time.
18 . The method according to claim 16 , wherein said (b) turning ON a responder channel, by the responder device, when the responder device detects the synchronization signal on the first pin after a first predetermined period of time.
19 . The method according to claim 17 , wherein said (b) turning ON a responder channel, by the responder device, when the responder device detects the synchronization signal on the first pin after a second predetermined period of time.
20 . The method according to claim 16 , wherein the generated synchronization signal is synchronous with a main switching clock signal of the requestor device.

Description

BACKGROUND DC/DC regulators operate by accepting an input DC voltage that may vary over a given range and output a constant DC voltage to provide a stable and reliable power supply. Fluctuations in power can lead to device malfunction or permanent circuit damage. DC/DC regulators ensure longevity and optimal functioning of many conventional electronic devices. Conventional DC/DC regulators may operate in buck mode (convert an input DC voltage to a lower DC voltage of the same polarity), boost mode (convert an input DC voltage to a higher DC voltage of the same polarity), or buck-boost mode (convert an input DC voltage to a lower or higher DC voltage of the same polarity). As power demands increase, single-phase converters reach their limitations in terms of current handling and efficiency. To counter these limitations, multiphase DCDC converters have been used to meet the increased power demands. Conventional multiphase converters employ multiple converter circuits operating in parallel, sharing the load current. The use of conventional multiphase converters increases current capability by distributing the load current across multiple phases, thereby increasing the overall current handling capacity of the converter. Moreover, the use of conventional multiphase converters reduces output ripple, wherein the phase-shifted operation of individual phases leads to a cancellation effect on the output ripple current, thereby having a cleaner and more stable output voltage and improving the performance of the powered devices. Additionally, conventional multiphase converters achieve higher efficiency compared to conventional single-phase converters due to reduced losses associated with lower RMS currents and better thermal management. Also, conventional multiphase converters, by sharing the load, allow for smaller components in each phase and a more compact overall design. On the other hand, conventional multiphase converters realize switching losses, wherein each phase in a multiphase converter has its own set of switching components, such as MOSFETs, which contribute to switching losses that become more prominent at low loads because the fixed losses are distributed over a smaller output power. Also, conventional multiphase converters realize gate driver losses, wherein gate drivers, which are responsible for turning the MOSFETs ON and OFF, contribute to losses at light loads where the switching frequency remains constant while the output power decreases. Moreover, conventional multiphase converters realize control circuit losses, wherein the circuitry responsible for controlling and synchronizing the phases consumes power that can become a significant portion of the total losses at low loads. Several conventional mitigation techniques can be employed to improve the efficiency of multiphase converters at low output loads. One conventional technique is known as phase shedding, where one or more phases are disabled when the required output power falls below a certain threshold. By reducing the number of active phases, switching and gate driver losses can be minimized. However, implementing this conventional technique introduces additional complexity and cost to the converter design due to additional control circuitry to manage the activation and deactivation of phases. For example, implementing conventional phase shedding presents the challenge of generating power thresholds within the integrated circuit, instead of sensing the input and output voltage of the DCDC converter. The generation of power thresholds within the integrated circuit is topology dependent. Another example of a challenge to implementing conventional phase shedding is the bi-directional communications between requestor and responder devices to achieve highest efficiency and dynamic performance on the regulated voltage. SUMMARY According to an aspect of the disclosure, a device includes an adaptive power limitation circuit configured to automatically determine active phases of a DCDC converter based upon power level of the DCDC converter. The adaptive power limitation circuit includes a translinear circuit configured to convert the power level of the DCDC converter to a current level; and a clamping circuit, operatively connected to the translinear circuit, configured to clamp a maximum current of the adaptive power limitation circuit to a predetermined value. According to another aspect of the disclosure, a system includes a DCDC converter; an adaptive power limitation circuit, operatively connected to the DCDC converter, configured to automatically determine active phases of the DCDC converter based upon power level of the DCDC converter; and a switch-mode controller, operatively connected to the DCDC converter and the adaptive power limitation circuit, configured to control a shedding of phases in the DCDC converter based upon a comparison between the generated current level and an inductor current of the DCDC converter. The adaptive power limit