US-20260128661-A1 - METHOD FOR MONITORING AND MANAGING CONDUCTION LOSSES IN AN ELECTRONIC CIRCUIT

US20260128661A1US 20260128661 A1US20260128661 A1US 20260128661A1US-20260128661-A1

Abstract

The invention relates to a method for monitoring and managing conduction losses in an electronic circuit comprising at least a first transistor (T 1 ) and a second transistor (T 2 ), the first transistor (T 1 ) and the second transistor (T 2 ) being coupled in parallel, said method comprising: a first step E 1 ) consisting in commanding the first transistor (T 1 ) so that it switches to a closed-circuit state, and in measuring a first time taken by the first transistor to close (Df_T1) following the command to switch said first transistor (T 1 ) to the closed-circuit state, a second step E 2 ) consisting in commanding the second transistor (T 2 ) so that it switches to a closed-circuit state, the command to switch the second transistor (T 2 ) to a closed-circuit state occurring after a first determined time TM 1 , a third step E 3 ) consisting in commanding the first transistor (T 1 ) so that it switches to an open-circuit state, and in measuring a first time taken by the first transistor to open (Do_T1) following the command to switch said first transistor (T 1 ) to an open-circuit state, a fourth step E 4 ) consisting in commanding the second transistor (T 2 ) so that it switches to an open-circuit state, the command to switch the second transistor (T 2 ) to an open-circuit state occurring after a second determined time TM 2.

Inventors

Jacques Rocher
Yannick Leroy

Assignees

Schaeffler Technologies AG & Co. KG

Dates

Publication Date: 20260507
Application Date: 20231128
Priority Date: 20221130

Claims (8)

1 . A method for monitoring and managing conduction losses in an electronic circuit comprising at least a first transistor (T 1 ) and a second transistor (T 2 ), the first transistor (T 1 ) and the second transistor (T 2 ) being coupled in parallel, said method comprising: a first step E 1 ) consisting in commanding the first transistor (T 1 ) so that it switches to a closed-circuit state, and in measuring a first time taken by the first transistor to close (Df_T 1 ) following the command to switch said first transistor (T 1 ) to the closed-circuit state, a second step E 2 ) consisting in commanding the second transistor (T 2 ) so that it switches to a closed-circuit state, the command to switch the second transistor (T 2 ) to a closed-circuit state occurring after a first determined time TM 1 , a third step E 3 ) consisting in commanding the first transistor (T 1 ) so that it switches to an open-circuit state, and in measuring a first time taken by the first transistor to open (Do_T 1 ) following the command to switch said first transistor (T 1 ) to an open-circuit state, a fourth step E 4 ) consisting in commanding the second transistor (T 2 ) so that it switches to an open-circuit state, the command to switch the second transistor (T 2 ) to an open-circuit state occurring after a second determined time TM 2 , a fifth step E 5 ) consisting in commanding the second transistor (T 2 ) so that it switches to a closed-circuit state, and in measuring a first time taken by the second transistor to close (Df_T 2 ) following the command to switch said second transistor (T 2 ) to the closed-circuit state, a sixth step E 6 ) consisting in commanding the first transistor (T 1 ) so that it switches to a closed-circuit state, the command to switch the first transistor (T 1 ) to a closed-circuit state occurring after a third determined time TM 3 , a seventh step E 7 ) consisting in commanding the second transistor (T 2 ) so that it switches to an open-circuit state, and in measuring a first time taken by the second transistor to open (Do_T 2 ) following the command to switch said second transistor (T 2 ) to an open-circuit state, an eighth step E 8 ) consisting in commanding the first transistor (T 1 ) so that it switches to an open-circuit state, the command to switch the first transistor (T 1 ) to an open-circuit state occurring after a fourth determined time TM 4 , a ninth step E 9 ) consisting in storing in a memory the values of the first time taken by the first transistor to close (Df_T 1 ), the first time taken by the first transistor to open (Do_T 1 ), the first time taken by the second transistor to close (Df_T 2 ), and the first time taken by the second transistor to open (Do_T 2 ), a tenth step E 10 ) consisting in executing steps E 1 ) to E 9 ) at least n times, and an eleventh step E 11 ) consisting in taking an average of the n measurements of the first time taken by the first transistor to close (Df_T 1 ), an average of the n measurements of the first time taken by the first transistor to open (Do_T 1 ), an average of the n measurements of the first time taken by the second transistor to close (Df_T 2 ), and an average of the n measurements of the first time taken by the second transistor to open (Do_T 2 ), a twelfth step E 12 ) consisting in performing steps E 1 ) to E 11 ) m times, and a thirteenth step E 13 ) consisting in comparing the m values of the respective n averaged values, wherein when at least one result of the comparison of the m values drifts from the average value by p% then generate a software alert and wherein when a result of the comparison of the m values of the n averaged values of the first time taken by the first transistor to close (Df_T 1 ), or the m values of the n averaged values of the first time taken by the first transistor to open (Do_T 1 ), or the m averaged values of the n values of the first time taken by the second transistor to close (Df_T 2 ), or the m averaged values of the n values of the first time taken by the second transistor to open (Do_T 2 ) drifts by p % then activate the transistor corresponding to the value that has drifted only after the other transistor.
2 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 1 , wherein if the observed drift of the m values of the n averaged values of said transistor activated only second continues a drift similar to that observed, for example of greater than p %, then activate a software alert.
3 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 2 , wherein if the drift of the m values of the n averaged values of said transistor activated only second has a drift of less than p % then activate said corresponding transistor first again.
4 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 1 , wherein the value of p % is equal to 10%.
5 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 4 , wherein if the drift of the m values of the n averaged values of said transistor activated only second has a drift of greater than p % then deactivate said transistor.
6 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 1 , wherein the processing function used is a mathematical three sigma method.
7 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 1 , wherein at least one of the two transistors is an IGBT transistor.
8 . The method for monitoring and managing conduction losses in an electronic circuit as claimed in claim 1 , wherein at least one of the two transistors is an SiC/GaN transistor.

Description

TECHNICAL FIELD The invention relates to the field of electric motor vehicles and more precisely to a method for monitoring and managing conduction losses in an electronic circuit. Prior Art An electric vehicle generally comprises at least one electric machine, for example an asynchronous electric motor, designed to make at least one wheel of the electric vehicle rotate. It also comprises at least one high-voltage battery, for example an 800 Volt battery, designed to provide electrical energy in order to supply power to the electric machine. In order to allow the electric motor to be supplied with electrical energy by the high-voltage battery, the electric vehicle also comprises an on-board charger (OBC) connected on the one hand to the high-voltage battery and on the other hand to an electrical supply network. The on-board charger makes it possible to convert an alternating voltage, provided by the electrical supply network, into a direct voltage to charge the battery. An on-board charger primarily comprises a power factor corrector (PFC) circuit, a DC-DC voltage converter, commonly called a “DC/DC converter”, and a microcontroller capable of commanding the power factor corrector circuit. In the case of charging the high-voltage battery, the power factor corrector circuit is the element of the on-board charger which converts the alternating voltage, provided by the electrical supply network, into a direct voltage. For example, in the case where the electrical supply network is a three-phase alternating voltage network, the power factor corrector circuit comprises three branches. Each branch, often called a cell, comprises two transistors coupled in series and each cell is coupled to one phase of the alternating voltage. As mentioned above in the description, the role of the power factor corrector circuit is to transform the alternating voltage into a direct voltage. To do this, the switches or transistors of a cell are commanded so as to switch in a determined order; the cells are themselves also commanded in a determined order so as to rectify the input signal to create a continuous signal at the output of the PFC. Since the power to be transferred is relatively high, each switch or transistor, during a change of state, incurs “switching” losses which, when they are repeated and not controlled, may cause significant heating of the switches and greatly reduce service life In order to reduce the power transferred by the transistors, document FR2114069 first of all proposes positioning another transistor in parallel. Thus, such an assembly ingeniously makes it possible to reduce the power per transistor. In order to limit switching losses, document FR2114069 also proposes an original command strategy for commanding the parallel transistors of a cell. The aim of this method is to first of all make a first transistor of the two transistors coupled in parallel switch and wait a determined time before commanding the second transistor. Thus, it is possible to reduce switching losses during switching of the second transistor. Specifically, since the first transistor is already switched, there is no switching loss for the second transistor. By virtue of this solution, it is possible to control the conduction losses of a switching cell comprising two transistors coupled in parallel. However, the fixed switching time and more particularly the time delay before switching the second transistor is not optimal with regard to the conduction losses of the first transistor which may cause a drift in the switching time representative of possible wear of said transistor. SUMMARY OF THE INVENTION The invention relates to a method for monitoring and managing conduction losses in an electronic circuit comprising at least a first transistor and a second transistor, the first transistor and the second transistor being coupled in parallel; said method has a first step E1) consisting in commanding the first transistor so that it switches to a closed-circuit state, and in measuring a first time taken by the first transistor to close following the command to switch said first transistor to the closed-circuit state, a second step E2) consisting in commanding the second transistor so that it switches to a closed-circuit state, the command to switch the second transistor to a closed-circuit state occurring after a first determined time TM1, a third step E3) consisting in commanding the first transistor so that it switches to an open-circuit state, and in measuring a first time taken by the first transistor to open following the command to switch said first transistor to an open-circuit state, a fourth step E4) consisting in commanding the second transistor so that it switches to an open-circuit state, the command to switch the second transistor to an open-circuit state occurring after a second determined time TM2, a fifth step E5) consisting in commanding the second transistor so that it switches to a closed-circuit state, and in measuri