US-20260128668-A1 - SEMICONDUCTOR DEVICE

US20260128668A1US 20260128668 A1US20260128668 A1US 20260128668A1US-20260128668-A1

Abstract

A semiconductor device for a power conversion circuit includes a first main terminal, a second main terminal, a signal terminal, a substrate, a semiconductor element and a snubber circuit. The substrate has an insulating base material, a first wiring disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring disposed on the one surface and electrically connected to the second main terminal. The semiconductor element is electrically connected to the first wiring. The snubber circuit includes a capacitor and electrically bridges the first wiring and the second wiring. The substrate has a signal wiring that is disposed between the semiconductor element and the snubber circuit and electrically connects the signal terminal and the semiconductor element.

Inventors

Chihiro Kato
Masayoshi Nishihata
Takahiro Hirano
Tomoaki MITSUNAGA
Yuri Imai
Satoshi Katayama
Yuto YAMAGUCHI

Assignees

DENSO CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260102
Priority Date: 20230705

Claims (15)

1 . A semiconductor device for a power conversion circuit, the semiconductor device comprising: a first main terminal; a second main terminal; a signal terminal; a substrate having an insulating base material, a first wiring disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring disposed on the one surface and electrically connected to the second main terminal; a semiconductor element electrically connected to the first wiring; and a snubber circuit including a capacitor and electrically bridging the first wiring and the second wiring, wherein the substrate has a signal wiring that is disposed between the semiconductor element and the snubber circuit and electrically connects the signal terminal and the semiconductor element.
2 . The semiconductor device according to claim 1 , wherein the semiconductor element is a first element, the semiconductor device further comprising: a second element, as another semiconductor element, connected in series to the first element and providing an upper and lower arm circuit together with the first element, wherein one of the first main terminal and the second main terminal is a positive terminal and the other of the first main terminal and the second main terminal is a negative terminal, the second element is electrically connected to the second wiring, and the snubber circuit is connected in parallel to the upper and lower arm circuit.
3 . The semiconductor device according to claim 2 , wherein the snubber circuit includes a plurality of the capacitors, the first main terminal, the first wiring, the capacitors, the second wiring and the second main terminal provide a plurality of current paths, and the plurality of current paths have an equal impedance.
4 . The semiconductor device according to claim 3 , wherein the plurality of current paths are disposed in line symmetry.
5 . The semiconductor device according to claim 4 , wherein the second main terminal includes two second main terminals, the two second main terminals are disposed on opposite sides of one first main terminal in a first direction orthogonal to a thickness direction of the substrate, the first element and the second element are arranged side by side in a second direction orthogonal to the thickness direction and the first direction, and the second wiring includes two second wirings that are disposed on opposite sides of the first wiring in the first direction.
6 . The semiconductor device according to claim 1 , wherein a capacitance of the capacitor is defined as C and a parasitic inductance of a main circuit portion connecting the snubber circuit and a smoothing capacitor is defined as Ldc, and the capacitance C is set to satisfy a relation of C/Ldc 0.004.
7 . The semiconductor device according to claim 1 , wherein the capacitor is joined to at least one of the first wiring and the second wiring.
8 . The semiconductor device according to claim 7 , further comprising: a thermal-conductive member that thermally connects the capacitor and a portion of the substrate other than a joined portion with the capacitor.
9 . The semiconductor device according to claim 1 , wherein the semiconductor element includes a plurality of semiconductor elements aligned in a predetermined direction, each of the plurality of semiconductor elements includes a main electrode and a drive command pad to command electrical conduction to the main electrode, and the plurality of semiconductor elements are arranged in an orientation so that the drive command pads are positioned closer to the signal wiring than the main electrodes.
10 . The semiconductor device according to claim 1 , further comprising: an upper arm element providing an upper arm of an upper and lower arm circuit; a lower arm element providing a lower arm of the upper and lower arm circuit; an upper arm metal plate joined to a main electrode of the upper arm element; and a lower arm metal plate joined to a main electrode of the lower arm element, wherein the semiconductor element is one of the upper arm element and the lower arm element, each of the upper arm metal plate and the lower arm metal plate has an adjacent portion adjacent to each other, the upper arm metal plate and the lower arm metal plate are disposed so that a direction of current flowing through the adjacent portion of the upper arm metal plate is opposite to a direction of current flowing through the adjacent portion of the lower arm metal plate.
11 . The semiconductor device according to claim 1 , further comprising: a plurality of interposing substrates on which passive components to suppress parasitic oscillations are mounted; and a connecting wiring electrically connecting the plurality of interposing substrates, wherein the signal wiring is provided by the plurality of interposing substrates and the connecting wiring.
12 . The semiconductor device according to claim 1 , wherein the snubber circuit includes a resistor connected in series with the capacitor, and the resistor is disposed closer to a center of the substrate than the capacitor.
13 . The semiconductor device according to claim 12 , further comprising: an interposing substrate providing the signal wiring, wherein the interposing substrate has a passive component to suppress a parasitic oscillation and a pad connected to the semiconductor element through a wire, and an upper end of the resistor is lower than a surface of the pad in a thickness direction of the substrate.
14 . The semiconductor device according to claim 1 , further comprising: an interposing substrate providing the signal wiring, wherein the interposing substrate has a passive component to suppress a parasitic oscillation and a pad connected to the semiconductor element through a wire, and the passive component is disposed at a position that is off an extension line of the wire connected to the pad on a projection plane defined orthogonal to a thickness direction of the substrate.
15 . The semiconductor device according to claim 1 , wherein the semiconductor element has a main electrode, a drive command pad that commands an electrical conduction to the main electrode, and a potential detection pad that outputs a signal for detecting a potential of the main electrode, the signal terminal includes a drive command terminal electrically connected to the drive command pad via the signal wiring, and a potential detection terminal electrically connected to the potential detection pad via the signal wiring, the drive command terminal, the signal wiring, and the potential detection terminal are disposed to provide a first current loop, the drive command pad, the potential detection pad, and the signal wiring are disposed to provide a second current loop, one of the first current loop and the second current loop is disposed to allow a current to flow therein in a direction to remove charge from the drive command pad with respect to a magnetic field caused by an electrical conduction to a main circuit, and the other of the first current loop and the second current loop is disposed to allow a current to flow therein in a direction to inject the charge into the drive command pad with respect to the magnetic field caused by the electrical conduction to the main circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation application of International Patent Application No. PCT/JP2024/020600 filed on Jun. 6, 2024, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2023-110769 filed on Jul. 5, 2023 and Japanese Patent Application No. 2024-071968 filed on Apr. 25, 2024. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD The present disclosure herein relates to a semiconductor device. BACKGROUND JP 2021-182575 A discloses a semiconductor device having a snubber circuit therein. Contents of the description of JP 2021-182575 A are incorporated herein by reference as a description of technical elements in this description. SUMMARY According to an aspect of the present disclosure, a semiconductor device includes a first main terminal, a second main terminal, a signal terminal, a substrate, a semiconductor element and a snubber circuit. The substrate has an insulating base material, a first wiring disposed on one surface of the insulating base material and electrically connected to the first main terminal, and a second wiring disposed on the one surface and electrically connected to the second main terminal. The semiconductor element is electrically connected to the first wiring. The snubber circuit includes a capacitor and electrically bridges the first wiring and the second wiring. The substrate may have a signal wiring that is disposed between the semiconductor element and the snubber circuit and electrically connects the signal terminal and the semiconductor element. BRIEF DESCRIPTION OF DRAWINGS Features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a circuit configuration of a power conversion device to which a semiconductor device according to a first embodiment is applied. FIG. 2 is a perspective view illustrating an example of a semiconductor module. FIG. 3 is a plan view of the semiconductor module. FIG. 4 is a cross-sectional view taken along a line IV-IV in FIG. 3. FIG. 5 is a plan view illustrating an example of the semiconductor device. FIG. 6 is a plan view illustrating a wiring pattern of a substrate. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view illustrating another example of the connection structure between a capacitor and the substrate. FIG. 9 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 10 is a cross-sectional view illustrating still another example of the connection structure between the capacitor and the substrate. FIG. 11 is a circuit diagram illustrating a verification model. FIG. 12 is a diagram illustrating a verification result. FIG. 13 is a diagram illustrating a temperature distribution. FIG. 14 is a diagram illustrating disposition of a current path formed by a snubber circuit. FIG. 15 is a plan view illustrating a modification example. FIG. 16 is a plan view illustrating another modification example. FIG. 17 is a plan view illustrating still another modification example. FIG. 18 is a plan view illustrating a semiconductor element in a semiconductor device according to a second embodiment. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a partial cross-sectional view of the semiconductor device and a semiconductor module. FIG. 21 is a plan view illustrating an example of a connection structure between a clip and the semiconductor element. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 21. FIG. 23 is a plan view illustrating another example of the connection structure between the clip and the semiconductor element. FIG. 24 is a perspective view illustrating the clip. FIG. 25 is a plan view illustrating another example of the clip. FIG. 26 is a plan view illustrating still another example of the clip. FIG. 27 is a cross-sectional view illustrating still another example of the clip. FIG. 28 is a plan view illustrating still another example of the clip. FIG. 29 is a plan view illustrating still another example of the connection structure between the clip and the semiconductor element. FIG. 30 is a cross-sectional view taken along a line XXX-XXX in FIG. 29. FIG. 31 is a plan view illustrating still another example of the clip. FIG. 32 is a plan view illustrating still another example of the clip. FIG. 33 is a plan view illustrating still another example of the clip. FIG. 34 is a plan view illustrating still another example of the clip. FIG. 35 is a plan view illustrating still another example of the clip. FIG. 36 is a plan view illustrating still another example of the clip. FIG. 37 is a plan view illustrating still another example of the clip. FIG. 38 is a plan view illustratin