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US-20260128672-A1 - High-Voltage Pulsed Power Generator with Flexible Output Pattern and Voltage Droop Compensation

US20260128672A1US 20260128672 A1US20260128672 A1US 20260128672A1US-20260128672-A1

Abstract

The present invention relates to high-voltage solid-state pulsed power generators and discloses a novel topology capable of producing multipulse high-voltage output with enhanced voltage gain using fewer energy storage elements and semiconductor switches, thereby improving system reliability and reducing component count. The architecture provides flexibility in adjusting key pulse parameters such as amplitude, width, and repetition rate, making it suitable for a wide range of applications. The generator features a modular and scalable design, allowing sub-circuits to be added or removed to meet varying load requirements. In addition, the invention discloses a method for compensating voltage droop in long-duration high-voltage pulses without requiring additional power supplies, energy storage devices, switching components, or complex control systems. The proposed method offers selectable levels of compensation, reduces system complexity and footprint, and provides a compact, reliable, and cost-effective solution for voltage droop mitigation in pulsed power applications.

Inventors

  • Devesh Malviya

Assignees

  • Devesh Malviya

Dates

Publication Date
20260507
Application Date
20251003
Priority Date
20241102

Claims (16)

  1. 1 . A high voltage solid-state pulsed power generator, comprising: a DC voltage source, a main switch (T S ), a load switch (T Py+1 ), and a plurality of sub-modules and sub-stages, wherein each sub-module comprises a capacitor (C SM ), a limiting resistor (r lim. ), and two controllable switches (T a & T b ), and each sub-stage comprises a capacitor (C SS ), a diode (D), and two controllable switches (T C & T P ).
  2. 2 . The generator of claim 1 , wherein the plurality of sub-modules are connected in series to form a sub-module chain, the sub-module chain being connected in parallel with a cascaded structure of sub-stages connected in parallel, wherein: (a) a positive terminal of the DC voltage source is connected to a collector of the main switch (T S ), an emitter of T S is connected to an emitter of switch, T 1a , an anode of diode D 1 , and collectors of switches, T 1b and T P1 ; (b) a collector of T 1a is connected to a terminal of capacitor, C SM1 through resistor, r lim. , the other terminal of C SM1 being connected to an emitter of T 1b , which is further connected to an emitter of T 2a and a collector of T 2b ; (c) a collector of T 2a is connected to a terminal of capacitor, C SM2 through resistor, r lim. , the other terminal of C SM2 being connected to an emitter of T 2b , which is further connected to an emitter of T 3a and a collector of T 3b ; (d) additional sub-modules are similarly connected, such that an emitter of the T b switch of the last sub-module (T xb ) and a terminal of its capacitor are connected to an emitter of T C1 , negative terminal of the DC voltage source, and ground; (e) a plurality of sub-stages is connected in parallel such that a cathode of a diode and a collector of a T C switch of a preceding sub-stage are connected to an anode of a diode and an emitter of a T C switch of an immediately succeeding sub-stage, respectively, and the cascaded sub-stages are further connected to the sub-module chain; (f) a load switch (T Py+1 ) is connected between a cathode of the diode of a last sub-stage and a resistive load (R), the other terminal of the load being connected to the ground.
  3. 3 . The generator of claim 1 , wherein the sub-module capacitors (C SM1 , C SM2 , . . . , C SMx ) are sequentially charged to the DC voltage source level (V S ), and thereafter connected in series to charge the sub-stage capacitors (C SS1 , C SS2 , . . . , C SSy ) through the T a switches of the sub-modules, the diodes of the sub-stages, and the T C switches of the sub-stages.
  4. 4 . The generator of claim 1 , wherein the sub-stage capacitors are charged to an enhanced voltage level up to a maximum of xV S , where x is the Number of Sub-Modules, and Wherein one or more sub-modules may be bypassed by turning OFF the corresponding T a switch, such that the charging path is completed through an anti-parallel diode of the T b switch of the bypassed sub-module.
  5. 5 . The generator of claim 1 , wherein a high-voltage pulse is generated by discharging the sub-module capacitors and the sub-stage capacitors in series into the load, the discharge path including all sub-module capacitors (C SM1 , C SM2 , . . . , C SMx ), sub-stage capacitors (C SS1 , C SS2 , . . . , C SSy ), T a switches (T 1a , T 2a , . . . , T xa ), T P switches (T P1 , T P2 , . . . , T Py ), the load switch (T Py+1 ), and the load (R), thereby generating a pulse magnitude of x(y+1)V S , where x and y are the number of sub-modules and sub-stages, respectively.
  6. 6 . The generator of claim 1 , wherein the output comprises a unipolar pulse with or without multiple sub-pulses within a single high-voltage pulse.
  7. 7 . The generator of claim 1 , wherein a multipulse output is generated by selectively preventing one or more sub-stage capacitors from discharging into the load during a portion of the pulse width by turning OFF the corresponding T P switch, thereby forward-biasing the corresponding diode to bypass the sub-stage capacitor and reducing the pulse magnitude by the capacitor's stored voltage.
  8. 8 . The generator of claim 1 , wherein a multipulse output is generated by selectively preventing one or more sub-module capacitors from discharging into the load during a portion of the pulse width by turning OFF the corresponding T a switch, thereby forward-biasing the anti-parallel diode of the corresponding T b switch to bypass the sub-module capacitor and reducing the pulse magnitude by the capacitor's stored voltage.
  9. 9 . The generator of claim 1 , wherein the pulse magnitude, width, and repetition rate are adjustable by controlling the discharge of stored energy from the capacitors through the controllable switches.
  10. 10 . The generator of claim 1 , wherein: the sub-module switches comprise insulated-gate bipolar transistors (IGBTs) with internal anti-parallel diodes or metal-oxide-semiconductor field-effect transistors (MOSFETs), and wherein, if IGBTs lack internal diodes, external anti-parallel diodes are connected across them; and the sub-stage switches comprise IGBTs without anti-parallel diodes, or MOSFETs each connected in series with an external diode, the external diode being connected such that a cathode of the diode is connected to a drain of the MOSFET or an anode of the diode is connected to a source of the MOSFET.
  11. 11 . A method of operating the generator of claim 1 to compensate for pulsed voltage droop, comprising employing the same pulse generator circuit elements to generate the high-voltage pulse and to perform voltage-droop compensation.
  12. 12 . The method of claim 11 , wherein the high-voltage pulse is generated by discharging all sub-stage capacitors (C SS1 , C SS2 , . . . C SSy ) in series into the load by turning ON all T P switches (T P1 , T P2 , . . . , T Py ), and the load switch, T Py+1 with all other switches OFF, thereby producing an output magnitude of xyV S .
  13. 13 . The method of claim 11 , wherein during pulse generation: (a) a collector of T 1b is connected to a collector of T P1 , whose emitter is connected to one terminal of C SS1 ; (b) another terminal of C SS1 is connected to a collector of T P2 , whose emitter is connected to one terminal of C SS2 ; (c) subsequent sub-stage capacitors (C SS3 . . . C SSy ) are similarly connected in series through their corresponding T P switches; and (d) the second terminal of the capacitor of the last sub-stage (C SSy ) is connected to the collector of the load switch, T Py+1 ; (e) an emitter of T Py+1 is connected to one terminal of load R, the other terminal of load R being connected through anti-parallel diodes of the T b (T 1b , T 2b , . . . , T xb ) switches, such that the pulse discharge path is completed while all the T a (T 1a , T 2a , . . . , T xa ), T b (T 1b , T 2b , . . . , T xb ), T C (T C1 , T C2 , . . . , T Cy ) switches and the main switch, T S remain OFF.
  14. 14 . The method of claim 11 , wherein voltage-droop compensation is achieved by discharging the sub-module capacitors (C SM1 , C SM2 , . . . , C SMx ) into the load sequentially during pulse generation, thereby compensating for voltage droop, the compensation effectiveness being enhanced with a greater number of sub-modules and sub-stages.
  15. 15 . The method of claim 11 , further comprising an intelligent feedback loop configured to monitor the pulsed output and control ON and OFF times of the T a switches to automatically compensate for voltage droop.
  16. 16 . The electrical connection formed during pulsed voltage droop compensation as claimed in claim 11 , wherein the electrical path dynamically changes multiple times during pulse generation, the number of such changes being equal to the selected level of compensation, such that: (a) at a first level of compensation, a sub-module capacitor (C SM1 ) discharges into the load, R through its corresponding T a switch while bypassing the anti-parallel diode of its associated T b switch; (b) at subsequent levels of compensation, additional sub-module capacitors (C SM2 . . . C SMx ) sequentially discharge into the load, R through their respective T a switches while bypassing the anti-parallel diodes of their respective T b switches; and (c) when only a subset of the total x sub-module capacitors is discharged, the compensation level corresponds to the number of capacitors engaged, whereas when all sub-module capacitors are discharged, the compensation level equals x.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority under 35 U.S.C. § 119(a) to Indian Patent Application No. 202411083854, filed on Nov. 2, 2024, the entire disclosure of which is hereby incorporated by reference. This application also claims priority under 35 U.S.C. § 119(a) to Indian Patent Application No. 202511061287, filed on Jun. 26, 2025, the entire disclosure of which is hereby incorporated by reference. Certified copies of the above-identified Indian patent applications will be made available to the United States Patent and Trademark Office (USPTO) via the World Intellectual Property Organization (WIPO) Digital Access Service (DAS). FIELD OF THE INVENTION The present invention relates to the field of power electronics; more particularly, it pertains to high-voltage solid-state pulsed power generators. The invention focuses on the design of a novel high-voltage pulsed power generator capable of producing multipulse output, and on the development of a method that compensates for voltage droop during pulsed operation while concurrently generating reliable, high-voltage pulses. BACKGROUND OF THE INVENTION Pulsed power generators are utilized across a wide range of applications, including medical technologies, defense systems, and scientific research. One emerging area of application is the food processing industry. Food, being perishable, is susceptible to spoilage and decay due to microbial contamination. Conventional preservation techniques, such as refrigeration, high-temperature pasteurization, and dehydration, often lead to a loss of nutritional value, natural taste, and flavor. To mitigate these drawbacks, non-thermal pulsed electric field (PEF) treatment has been proposed. This approach has been addressed, for example, in U.S. Pat. No. 5,690,978 and Canadian Patent No. 2,325,691. Various experimental studies have confirmed that applying short-duration, high-voltage pulses can inactivate microorganisms and enzymes responsible for food spoilage. Additionally, it has been shown that PEF treatment preserves food quality. Subsequent studies indicate that high-voltage multipulse output can further enhance the efficiency of PEF-based sterilization and reduce power consumption. Such multipulse waveforms are typically obtained by superimposing narrow pulses onto wider pulses. While wide pulses may cause continuous electrical breakdown in air, necessitating more robust generator designs, narrow pulses alone may lack sterilization efficacy. The concept of multipulse generation has been introduced to balance these trade-offs and meet the evolving requirements of food processing applications. Several multipulse generator topologies have been proposed in the literature. In “Analysis and Design of a Soft-Switching Interleaved Forward Converter for Generating Pulsed Electric Fields,” Proc. 25th Int. Telecommun. Energy Conf, pp. 705-712, October 2003, a soft-switching interleaved forward converter with an additional filter inductor is described, resulting in increased bulk and weight. Another approach, disclosed in “Wide Pulse Combined with Narrow-Pulse Generator for Food Sterilization,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 741-748, February 2008, combines a high step-up forward converter, a narrow pulse generator, and a full-bridge inverter. While effective in reducing power consumption, this configuration subjects the inverter switches to full pulse voltage stress, increasing component-level demands. An alternative design is presented in “High-Voltage Pulsed Power Supply to Generate Wide Pulses Combined with Narrow Pulses,” IEEE Trans. Plasma Sci., vol. 42, no. 7, pp. 1894-1901, July 2014. This system integrates a capacitor-diode voltage multiplier with a resonant circuit, allowing for high-voltage gains by charging capacitors progressively to higher voltages at higher stages. However, the maximum achievable voltage is limited by the ratings of available power electronics switches and passive components. Outside the food industry, long-duration high-voltage pulses are essential in specialized scientific applications, such as particle accelerators. These systems require high-voltage, unipolar pulses in the range of hundreds of kilovolts with durations spanning hundreds of microseconds to several milliseconds. One such requirement is highlighted in “Long Pulse Modulators,” Proc. CAS-CERN Accelerator School: Power Converters, pp. 217-244, May 2014. A significant challenge in these systems is voltage droop during the output pulse. Various compensation techniques have been proposed to address this issue. One conventional solution involves the use of a bouncer circuit, as described in “Development of All-Solid-State Bouncer Compensated Long Pulse Modulators for LEP 1 MW Klystrons to be Used for the LINAC4 Project at CERN,” Proc. 14th Linear Accel. Conf, pp. 984-986, October 2008. This method uses passive LC ringing to correct the droop, but results in large and expensive systems with