US-20260128674-A1 - SIGNAL DELAY SETTING CIRCUIT, ISOLATION INTEGRATED CIRCUIT AND POWER CONVERSION CIRCUITRY

US20260128674A1US 20260128674 A1US20260128674 A1US 20260128674A1US-20260128674-A1

Abstract

The present disclosure provides a signal delay setting circuit, an isolation integrated circuit and a power conversion circuitry. The isolation integrated circuit includes a primary side circuit, an isolation circuit and a secondary side circuit. The primary side circuit generates a primary side signal according to a first input signal and a second input signal. The isolation circuit converts the primary side signal into a secondary side signal. The secondary side circuit receives the secondary side signal through the isolation circuit, to generate an output signal. The signal delay setting circuit is coupled to the secondary side circuit, calculates a delay time according to a voltage difference between an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, and delays the secondary side signal according to the delay time, to control the duty ratio of the output signal.

Inventors

Jui Teng CHAN
Yong Cyuan CHEN
Jo-Yu Wang
Chih-Yuan Hsu
Chung-Kang WU

Assignees

POWERX SEMICONDUCTOR CORPORATION

Dates

Publication Date: 20260507
Application Date: 20260107
Priority Date: 20231024

Claims (20)

1 . A signal delay setting circuit applicable to an isolation integrated circuit, wherein the isolation integrated circuit comprises a primary side circuit, an isolation circuit, and a secondary side circuit, and the secondary side circuit is coupled to an alternative terminal and a secondary side ground terminal of the isolation integrated circuit and generates an output signal according to a secondary side signal, the isolation circuit is configured to convert a primary side signal from the primary side circuit into the secondary side signal, and the signal delay setting circuit comprises: a voltage drop generating circuit, coupled to the alternative terminal and the secondary side ground terminal, and configured to generate a voltage difference between the alternative terminal and the secondary side ground terminal; and a signal delay circuit, configured to shift the secondary side signal received by the secondary side circuit from the isolation circuit according to the voltage difference, so as to control a duty ratio of the output signal.
2 . The signal delay setting circuit according to claim 1 , wherein the voltage drop generating circuit comprises: a resistor component, coupled between the alternative terminal and the secondary side ground terminal; and a current generating circuit, coupled with the resistor component at the alternative terminal, configured to receive a secondary side power voltage provided to the secondary side circuit, and configured to output a detection current flowing through the resistor component according to the secondary side power voltage, so that the voltage difference is generated between the alternative terminal and the secondary side ground terminal.
3 . The signal delay setting circuit according to claim 2 , wherein the resistor component is arranged outside the isolation integrated circuit, and the current generating circuit is arranged inside the isolation integrated circuit.
4 . The signal delay setting circuit according to claim 1 , wherein the signal delay circuit is integrated into a control logic circuit of the secondary side circuit, and the voltage drop generating circuit is coupled to the control logic circuit via a buffer gate.
5 . The signal delay setting circuit according to claim 1 , wherein the signal delay circuit is configured to shift a plurality of rising edges of the secondary side signal according to the voltage difference.
6 . The signal delay setting circuit according to claim 1 , further comprising a delay time calculation circuit, configured to obtain a delay time according to the voltage difference, wherein the signal delay circuit is coupled to the delay time calculation circuit and configured to delay the secondary side signal by the delay time.
7 . The signal delay setting circuit according to claim 1 , wherein the secondary side circuit is configured to receive a secondary side power voltage via a secondary side power terminal of the isolation integrated circuit, and the voltage drop generating circuit is configured to generate the voltage difference when the secondary side power voltage exceeds a power-on reset voltage.
8 . The signal delay setting circuit according to claim 7 , wherein the signal delay circuit is configured to shift the secondary side signal according to the voltage difference when the secondary side power voltage exceeds an undervoltage lockout voltage, wherein the undervoltage lockout voltage is greater than the power-on reset voltage.
9 . An isolation integrated circuit, comprising: a primary side circuit, configured to generate a primary side signal; an isolation circuit, coupled to the primary side circuit, and configured to convert the primary side signal into a secondary side signal; a secondary side circuit, coupled to the isolation circuit, and configured to receive the secondary side signal via the isolation circuit, generate an output signal according to the secondary side signal, and receive a secondary side power voltage; and a signal delay setting circuit, coupled to the secondary side circuit and an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, and configured to obtain a voltage difference between the alternative terminal and the secondary side ground terminal when the secondary side power voltage exceeds a predetermined voltage and shift the secondary side signal according to the voltage difference to control a duty ratio of the output signal.
10 . The isolation integrated circuit according to claim 9 , wherein the signal delay setting circuit comprises: a voltage drop generating circuit, coupled to the alternative terminal and the secondary side ground terminal, and configured to receive the secondary side power voltage and generate the voltage difference between the alternative terminal and the secondary side ground terminal when the secondary side power voltage exceeds the predetermined voltage; and a signal delay circuit, configured to shift the secondary side signal according to the voltage difference.
11 . The isolation integrated circuit according to claim 10 , wherein the voltage drop generating circuit comprises: a resistor component, coupled between the alternative terminal and the secondary side ground terminal; and a current generating circuit, coupled with the resistor component at the alternative terminal, and configured to output a detection current to flow through the resistor component according to the secondary side power voltage exceeding the predetermined voltage, so that the voltage difference is generated between the alternative terminal and the secondary side ground terminal.
12 . The isolation integrated circuit according to claim 11 , wherein the resistor component is arranged outside the isolation integrated circuit, and the current generating circuit is arranged inside the isolation integrated circuit.
13 . The isolation integrated circuit according to claim 10 , wherein the secondary side circuit comprises a control logic circuit and a first buffer gate, the signal delay circuit is integrated into the control logic circuit, and the voltage drop generating circuit is coupled to the control logic circuit via the first buffer gate.
14 . The isolation integrated circuit according to claim 13 , wherein the secondary side circuit further comprises an amplifier circuit, and the amplifier circuit is coupled to the control logic circuit, and a secondary side power terminal and a signal output terminal of the isolation integrated circuit, and is configured to amplify the secondary side signal being shifted to generate the output signal to the signal output terminal.
15 . The isolation integrated circuit according to claim 13 , wherein the secondary side circuit further comprises a receiving circuit and an undervoltage lockout circuit; the receiving circuit is coupled to the isolation circuit, the undervoltage lockout circuit, and the control logic circuit; and the undervoltage lockout circuit is coupled to a secondary side power terminal of the isolation integrated circuit, and is configured to enable the receiving circuit to transmit the secondary side signal to the control logic circuit when the secondary side power voltage exceeds a protection voltage greater than the predetermined voltage.
16 . The isolation integrated circuit according to claim 15 , wherein the receiving circuit comprises a second buffer gate and an AND gate, the second buffer gate is coupled to the isolation circuit and a first input terminal of the AND gate, the undervoltage lockout circuit is coupled to a second input terminal of the AND gate, and the control logic circuit is coupled to an output terminal of the AND gate.
17 . The isolation integrated circuit according to claim 10 , wherein the signal delay circuit is configured to shift a plurality of rising edges of the secondary side signal according to the voltage difference.
18 . The isolation integrated circuit according to claim 10 , wherein the signal delay setting circuit further comprises a delay time calculation circuit, configured to obtain a delay time according to the voltage difference, and wherein the signal delay circuit is coupled to the delay time calculation circuit and configured to delay the secondary side signal by the delay time.
19 . The isolation integrated circuit according to claim 10 , wherein the predetermined voltage is a power-on reset voltage, and the signal delay circuit is configured to shift the secondary side signal according to the voltage difference when the secondary side power voltage exceeds an undervoltage lockout voltage, wherein the undervoltage lockout voltage is greater than the power-on reset voltage.
20 . A power conversion circuitry, comprising: a high-side switch; a low-side switch; a controller circuit, configured to output a first input signal and a second input signal; a first isolation integrated circuit, coupled between the controller circuit and the high-side switch, and comprising a first signal delay setting circuit, a first alternative terminal, and a first secondary side ground terminal, wherein the first isolation integrated circuit is configured to receive the first input signal and the second input signal, to generate a first output signal for driving the high-side switch; and a second isolation integrated circuit, coupled between the controller circuit and the low-side switch, and comprising a second signal delay setting circuit, a second alternative terminal, and a second secondary side ground terminal, wherein the second isolation integrated circuit is configured to receive the second input signal and the first input signal, to generate a second output signal for driving the low-side switch, wherein when a first secondary side power voltage received by the first isolation integrated circuit and a second secondary side power voltage received by the second isolation integrated circuit exceed a predetermined voltage, the first signal delay setting circuit obtains a first voltage difference between the first alternative terminal and the first secondary side ground terminal, and the second signal delay setting circuit obtains a second voltage difference between the second alternative terminal and the second secondary side ground terminal, and wherein when the first secondary side power voltage and the second secondary side power voltage exceed a protection voltage greater than the predetermined voltage, the first signal delay setting circuit shifts a first secondary side signal, which is generated by the first isolation integrated circuit according to the first input signal and the second input signal, according to the first voltage difference to control a duty ratio of the first output signal, and the second signal delay setting circuit shifts a second secondary side signal, which is generated by the second isolation integrated circuit according to the first input signal and the second input signal, according to the second voltage difference to control a duty ratio of the second output signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation application of U.S. application Ser. No. 18/412,623, filed Jan. 15, 2024, which claims priority to Taiwan Application Serial Number 112140656, filed Oct. 24, 2023, which is herein incorporated by reference in its entirety. BACKGROUND Field of Disclosure The present disclosure relates to a signal delay setting circuit, and in particular, to a signal delay setting circuit applicable to an isolation integrated circuit. Description of Related Art In a circuit structure including a high-side switch and a low-side switch, it is usually necessary to alternately turn on the high-side switch and the low-side switch to complete an operation. However, the high-side switch and the low-side switch may be turned on at the same time due to some non-ideal factors, which leads to a high current flow that may cause damage to the high-side switch and the low-side switch. Some related art techniques ensure that the high-side switch and low-side switch are not turned on at the same time by using RC circuit settings or using trimming methods to generate a dead zone or dead time. However, each of these related art techniques has its own disadvantages. For example, a dead time generated using techniques related to an RC circuit may have a high deviation due to physical characteristics of a resistor and/or a capacitor. For example, related art techniques using trimming methods may increase the complexity of the entire system. Therefore, it is necessary to propose a novel approach to address the aforementioned issues. SUMMARY One aspect of the present disclosure is a signal delay setting circuit applicable to an isolation integrated circuit. The isolation integrated circuit includes a primary side circuit, an isolation circuit, and a secondary side circuit. The isolation circuit is configured to convert a primary side signal from the primary side circuit into a secondary side signal, and the secondary side circuit is coupled to an alternative terminal and a secondary side ground terminal of the isolation integrated circuit. The signal delay setting circuit includes a voltage drop generating circuit, a delay time calculation circuit, and a signal delay circuit. The voltage drop generating circuit is coupled to the alternative terminal and the secondary side ground terminal, and generates a voltage difference between the alternative terminal and the secondary side ground terminal. The delay time calculation circuit is coupled to the voltage drop generating circuit, and calculates a delay time according to the voltage difference. The signal delay circuit is coupled to the delay time calculation circuit, and delays the secondary side signal received by the secondary side circuit from the isolation circuit according to the delay time, so as to control a duty ratio of an output signal generated by the secondary side circuit according to the secondary side signal, where the primary side signal is generated by the primary side circuit according to a first input signal and a second input signal. One aspect of the present disclosure is an isolation integrated circuit. The isolation integrated circuit includes a primary side circuit, an isolation circuit, a secondary side circuit, and a signal delay setting circuit. The primary side circuit receives a first input signal and a second input signal and generates a primary side signal according to the first input signal and the second input signal. The isolation circuit is coupled to the primary side circuit, and converts the primary side signal into a secondary side signal. The secondary side circuit is coupled to the isolation circuit, receives the secondary side signal via the isolation circuit, generates an output signal according to the secondary side signal, and receives a secondary side power voltage. The signal delay setting circuit is coupled to the secondary side circuit and an alternative terminal and a secondary side ground terminal of the isolation integrated circuit, detects a voltage difference between the alternative terminal and the secondary side ground terminal when the secondary side power voltage exceeds a predetermined voltage, calculates a delay time according to the voltage difference, and delay the secondary side signal according to the delay time to control a duty ratio of the output signal. One aspect of the present disclosure is a power conversion circuitry. The power conversion circuitry includes a high-side switch, a low-side switch, a controller circuit, a first isolation integrated circuit, and a second isolation integrated circuit. The controller circuit outputs a first input signal and a second input signal. The first isolation integrated circuit is coupled between the controller circuit and the high-side switch, includes a first signal delay setting circuit, a first signal input terminal, a second signal input terminal, a first alternative terminal, and a first secondary side ground termina