US-20260128681-A1 - MULTILEVEL INVERTER SYSTEM INCLUDING X-TYPE MULTILEVEL CONVERTERS HAVING MUTUAL INDUCTANCE CANCELLATION

US20260128681A1US 20260128681 A1US20260128681 A1US 20260128681A1US-20260128681-A1

Abstract

A multi-phase power inverter for an electric propulsion system including a plurality of X-type multilevel power converters arranged as solid-state integrated circuits. Each X-type multilevel power converter includes a positive direct current (DC) power bus, a negative DC power bus, a first alternating current (AC) bus, a second AC power bus, a first clamping diode, a second clamping diode, a power module substrate disposed on an insulating substrate, and a heat sink adjacent to a first side of the insulating substrate. The power module substrate includes a plurality of semiconductor switches, each including a plurality of lateral semiconductor dies each having gate control terminals. The plurality of semiconductor switches, the first clamping diode, and the second clamping diode are coplanar, with the DC power terminals on one side of the X-type multilevel power converter, and the auxiliary and output terminals disposed on the opposite side.

Inventors

Benjamin S. Ngu
Chandra S. Namuduri
Yilun Luo
Khorshed Mohammed Alam
Rashmi Prasad
Richard M. Nichols, III

Assignees

GM Global Technology Operations LLC

Dates

Publication Date: 20260507
Application Date: 20241106

Claims (20)

1 . A multi-phase power inverter for an electric propulsion system, the multi-phase power inverter comprising: a plurality of X-type multilevel power converters arranged to transfer electric power between a high-voltage direct current (DC) power source and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a first alternating current (AC) bus; a second AC power bus; a first clamping diode; a second clamping diode; a power module substrate disposed on an insulating substrate; a heat sink adjacent to a first side of the insulating substrate; and wherein the power module substrate includes: a plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node; wherein the first clamping diode is connected between the third node and the fourth node; wherein the second clamping diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC power bus; wherein the fifth node is connected to the second AC power bus; wherein each of the plurality of semiconductor switches includes a plurality of lateral semiconductor dies, and wherein each of the plurality of lateral semiconductor dies includes gate control terminals; and wherein the plurality of semiconductor switches, the first clamping diode, and the second clamping diode are coplanar.
2 . The multi-phase power inverter as recited in claim 1 , wherein the first AC power bus and the second AC power bus are coplanar.
3 . The multi-phase power inverter as recited in claim 1 , wherein the first AC power bus and the second AC power bus are parallel to one another.
4 . The multi-phase power inverter as recited in claim 1 , wherein the first AC power bus and the second AC power bus are laminated.
5 . The multi-phase power inverter as recited in claim 1 , wherein the positive DC power bus and the negative DC power bus are parallel to one another.
6 . The multi-phase power inverter as recited in claim 1 , wherein each of the first AC power bus, the second AC power bus, the positive DC power bus, and the negative DC power bus extend past a top edge of the X-type multilevel power converter.
7 . The multi-phase power inverter as recited in claim 1 , wherein the positive DC power bus and the negative DC power bus extend past a top edge of the X-type multilevel power converter, and wherein the first AC power bus and the second AC power bus extend past a bottom edge of the X-type multilevel power converter.
8 . The multi-phase power inverter as recited in claim 1 , wherein the positive DC power bus and the negative DC power bus extend past a top edge of the X-type multilevel power converter, and wherein the first AC power bus and the second AC power bus extending perpendicular to the X-type multilevel power converter from a middle portion of the X-type multilevel power converter.
9 . The multi-phase power inverter as recited in claim 1 , wherein interconnections include one or more of wire bonding, ribbon bonding, clip bonding, and direct copper bus bonding.
10 . A multi-phase power inverter for an electric propulsion system, the multi-phase power inverter comprising: a plurality of X-type multilevel power converters arranged to transfer electric power between a high-voltage direct current (DC) power source and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a first alternating current (AC) bus; a first auxiliary bus; a second auxiliary bus; a plurality of semiconductor switches disposed on an insulating substrate board, the plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, and a fourth semiconductor switch; a heat sink adjoined to the insulating substrate board via a thermally conductive interface material; wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the first node is connected to the first auxiliary bus; wherein the second node is connected to the first AC power bus; and wherein the third node is connected to the second auxiliary bus.
11 . The multi-phase power inverter as recited in claim 10 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first auxiliary bus, and the second auxiliary bus are arranged in sections including: a first section composed of the first AC power bus; a second section composed of the second semiconductor switch arranged coplanar with the third semiconductor switch; a third section composed of the first auxiliary bus arranged coplanar with the second auxiliary bus; a fourth section composed of the first semiconductor switch arranged coplanar with the fourth semiconductor switch; a fifth section composed of the positive DC power bus arranged coplanar with the negative DC power bus; wherein the first section is adjacent to the second section that is adjacent to the third section that is adjacent to the fourth section that is adjacent to the fifth section; and wherein the first AC power bus is arranged parallel to the positive DC power bus and the negative DC power bus.
12 . The multi-phase inverter as recited in claim 11 , further including: a first gate control arranged between the first section and the second section, the first gate control being disposed adjacent to the first AC power bus and the third semiconductor switch; a second gate control arranged between the second section and the third section, the second gate control being disposed adjacent to the second semiconductor switch and the first auxiliary bus; a third gate control arranged between the third section and the fourth section, the third gate control being disposed adjacent to the second auxiliary bus and the fourth semiconductor switch; a fourth gate control arranged between the fourth section and the fifth section, the fourth gate control being disposed adjacent to the first semiconductor switch and the positive DC power bus; and wherein the first gate control is arranged coplanar with the second gate control that is arranged coplanar with the third gate control that is arranged coplanar with the fourth gate control.
13 . The multi-phase power inverter as recited in claim 10 , further including: a third auxiliary bus connected to a fourth node; and a first clamping diode, and a second clamping diode; wherein the first clamping diode is connected between the first node and the fourth node; and wherein the second clamping diode is connected between the fourth node and the third node.
14 . The multi-phase power inverter as recited in claim 13 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first auxiliary bus, the second auxiliary bus, the third auxiliary bus are arranged in sections including: a first section composed of the negative DC power bus; a second section composed of the fourth semiconductor switch and the second clamping diode; a third section composed of the third semiconductor switch, the first AC power bus, and the third auxiliary bus; a fourth section composed of the second semiconductor switch and the first clamping diode; and a fifth section composed of the first semiconductor switch and the positive DC power bus; wherein the first section is adjacent to the second section that is adjacent to the third section that is adjacent to the fourth section that is adjacent to the fifth section; and wherein the first AC power bus is arranged parallel to the positive DC power bus and the negative DC power bus.
15 . The multi-phase power inverter as recited in claim 14 , further including: a first gate control arranged adjacent to the fourth semiconductor switch; a second gate control arranged adjacent to the third semiconductor switch; a third gate control arranged adjacent to the second semiconductor switch; and a fourth gate control arranged adjacent to the first semiconductor switch, wherein the first gate control is arranged coplanar with the second gate control that is arranged coplanar with the third gate control that is arranged coplanar with the fourth gate control.
16 . The multi-phase power inverter as recited in claim 10 , further including: a first clamping diode and a second clamping diode; a second AC power bus; wherein the plurality of semiconductor switches further includes: a fifth semiconductor switch; a sixth semiconductor switch; a seventh semiconductor switch; and an eighth semiconductor switch; wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node; wherein the first clamping diode is connected between the third node and the fourth node; wherein the second clamping diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC power bus; and wherein the fifth node is connected to the second AC power bus.
17 . The multi-phase inverter as recited in claim 16 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC power bus, the second AC power bus, the first clamping diode, and the second clamping diode are arranged into a plurality of sections including: a first section composed of the negative DC power bus; a second section composed of the fourth semiconductor switch arranged coplanar with the second clamping diode that is arranged coplanar with the eighth semiconductor switch; a third section composed of the third semiconductor switch arranged coplanar with the seventh semiconductor switch; a fourth section composed of the first AC power bus and the second AC power bus; a fifth section composed of the second semiconductor switch arranged coplanar with the first clamping diode that is arranged coplanar with the sixth semiconductor switch; a sixth section composed of the first semiconductor switch arranged coplanar with the fifth semiconductor switch; a seventh section composed of the positive DC power bus; wherein the first section is adjacent to the second section that is adjacent to the third section that is adjacent to the fourth section that is adjacent to the fifth section that is adjacent to the sixth section; and wherein the first AC power bus and the second AC power bus are arranged parallel to the positive DC power bus and the negative DC power bus.
18 . The multi-phase inverter as recited in claim 17 , further including a plurality of gate control including: a first gate control arranged adjacent to the fourth semiconductor switch; a second gate control arranged adjacent to the third semiconductor switch; a third gate control arranged adjacent to the second semiconductor switch; a fourth gate control arranged adjacent to the first semiconductor switch; a fifth gate control arranged adjacent to the fifth semiconductor switch; a sixth gate control arranged adjacent to the sixth semiconductor switch; a seventh gate control arranged adjacent to the seventh semiconductor switch; an eighth gate control arranged adjacent to the eighth semiconductor switch; and wherein the first gate control is arranged coplanar with the second gate control that is arranged coplanar with the third gate control that is arranged coplanar with the fourth gate control that is coplanar with the fifth gate control that is coplanar with the sixth gate control that is coplanar with the seventh gate control that is coplanar with the eighth gate control.
19 . An electrified vehicle comprising: an electric propulsion system including: an electric motor configured to provide power to the electric propulsion system; a plurality of X-type multilevel power converters arranged to transfer electric power between a high-voltage direct current (DC) power source and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC) including: a positive DC power bus; a negative DC power bus; a first alternating current (AC) bus; a second AC power bus; a first clamping diode; a second clamping diode; a power module substrate disposed on an insulating substrate; a heat sink adjacent to a first side of the insulating substrate; and wherein the power module substrate includes: a plurality of semiconductor switches including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch, and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node; wherein the first clamping diode is connected between the third node and the fourth node; wherein the second clamping diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC power bus; wherein the fifth node is connected to the second AC power bus; wherein each of the plurality of semiconductor switches includes a plurality of lateral semiconductor dies, and wherein each of the plurality of lateral semiconductor dies includes gate control terminals; and wherein the plurality of semiconductor switches, the first clamping diode, and the second clamping diode are coplanar.
20 . The multi-phase power inverter as recited in claim 1 , wherein the first AC power bus and the second AC power bus are parallel to one another.

Description

The concepts described herein relate generally to vehicles employing electrified powertrain or propulsion systems, which are composed with direct current (DC) power supplies that provide DC electric power, which is converted to alternating current (AC) electric power via multi-phase power inverters, to control operation of one or multiple electric machines. High-voltage and high-power multilevel inverters (MLIs) have gained attention as the transportation electrification trend of consumer and commercial vehicles is rapidly expanding towards high-capacity mass transit systems such as electric aircraft, trains, and ships. MLIs such as neutral point clamped (NPC) and T-type inverters provide high-voltage and high-power operation capabilities but include stacked DC-link capacitors with a neutral point connection for zero voltage vector. This neutral point connection to the stacked DC-link capacitor may generate a neutral current oscillating at three times the fundamental frequency, which may cause capacitor voltage imbalance and overvoltage stress on capacitors and switching devices. A multi-phase inverter circuit may generate an inherent power loop in which high current flows from a DC-link capacitor to a high-side of the multilevel power inverter, then to a low-side of the multilevel power inverter and back. The power loop may generate a magnetic field, which forms parasitic inductance. As multi-phase power inverters may operate at higher switching frequencies, even small levels of parasitic inductance may lead to issues, for example, but not limited to, ringing and/or electromagnetic interference (EMI). The current flow path determines the size of the power loop, which determines the size of the magnetic field generated, and hence the size of the parasitic inductance. The current flow path is defined by the topology of the circuit, and therefore the topology of the circuit may affect the size of the parasitic inductance. As an X-type multilevel inverter can include a current flow path through a pair of external X-diodes, a length of the power loop is increased resulting in increased parasitic inductance. SUMMARY In view of the above discussion, it is useful to develop a system of integrating power semiconductor devices including selective active and passive vertical and/or lateral semiconductor dies to effect mutual inductance cancellation for a multi-phase power inverter including a plurality of X-type multilevel power converters having a topology that reduces parasitic inductance within the multi-phase power inverter and/or within each X-type multilevel power converter. The concepts disclosed herein relate to a system for a multi-phase power inverter including a plurality of X-type multilevel power converters that achieve mutual inductance cancellation. Such a system may be used in vehicles having an electrified propulsion system, for example, but not limited to, a motor vehicle having an electrified powertrain or propulsion system, e.g., an electric vehicle (EV) or plug-in hybrid electric vehicle (PHEV), or another mobile platform, which may be powered by an electric propulsion system, to reduce parasitic inductance within the multi-phase power inverter. Each multi-phase power inverter may include a plurality of X-type multilevel power converters arranged between a high-voltage direct current (DC) power source and an electric machine. The number of X-type multilevel power converters required is application specific. Each X-type multilevel power converter may be configured as a solid-state integrated circuit (IC) that includes a plurality of circuit components, for example, but not limited to semiconductor switches and busbars, which are connected to form a network of interconnections through which current may flow. The form of this network of interconnected circuitry is called a circuit topology. The concepts described herein provide a multi-phase power inverter that is advantageously arranged to minimize stray inductance and loop inductance employing magnetic field cancellation. This includes using cancelling fields by arranging positive, neutral and negative buses and a plurality of X-type multilevel power converters arranged in solid-state integrated circuits having laterally sectioned elements. The arrangement of the X-type multilevel power converters with laterally sectioned elements enables either single-sided or double-sided cooling to reduce thermal impedance. This configuration may serve to reduce stray inductance, thus leading to lower switching loss, less ringing, less electromagnetic interference (EMI), and lower device thermal stress. A multi-phase power inverter may include a plurality of X-type multilevel power converters arranged to transfer electric power between a high-voltage direct current (DC) power source and an electric machine. Each of the plurality of X-type multilevel power converters may be configured as a solid-state integrated circuit (IC). The at least one X-type multilevel p