US-20260128699-A1 - PULSE WIDTH MODULATION SIGNAL GENERATOR AND METHOD

US20260128699A1US 20260128699 A1US20260128699 A1US 20260128699A1US-20260128699-A1

Abstract

A semiconductor device for generating PWM modulation signals, for example an optimized pulse pattern OPP is provided. An ADC 42 outputs the angle of the motor, and is connected to a coprocessor 52 for example a digital signal processor DSP. The coprocessor 52 has an observer 44 connected to the angle inputs for generating a motor angle and a look up table 48 for generating a PWM signal as a direct function of the generated motor angle A PWM signal is output to timer unit 50 . A calculating unit 46 has an input connected to the coprocessor 52 , the calculating unit being arranged to select a look up table based on the generated motor angle and to store the selected look up table as the look up table 48.

Inventors

Mihail Jefremow
Jürgen Schäfer
Alberto Trentin
Klaus Scheibert
Arndt Voigtländer
Michael Augustin

Assignees

INFINEON TECHNOLOGIES AG

Dates

Publication Date: 20260507
Application Date: 20251030
Priority Date: 20241106

Claims (17)

1 . A semiconductor device for generating a pulse pattern, signal, comprising: an analog to digital converter, ADC, for connection to a motor, having an output for indicating the angle of the motor, a coprocessor having an angle input connected to the output of the ADC, an observer connected to the angle input for determining a motor angle, a coprocessor look up table for generating a pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and a calculating unit having an input connected to the coprocessor, the calculating unit being arranged to select a look up table from a plurality of look up tables based on the determined motor conditions e.g. like acceleration and torque and to store the selected look up table as the coprocessor look up table in the coprocessor.
2 . A semiconductor device according to claim 1 , further comprising a memory storing the plurality of look up tables and a direct memory access device (DMA) unit for loading a look up table selected by the calculating unit directly into the coprocessor as the coprocessor look up table.
3 . A semiconductor device according to claim 1 or 2 , wherein the observer comprises a loop output connected to the calculating unit, and is arranged: to further determine a motor speed; to output the determined motor speed and the determined motor angle through the loop output to the calculating unit; and to output the angle to the look up table; wherein the calculating unit is arranged to select the look up table based on the determined motor angle and the determined motor speed.
4 . A semiconductor device according to any preceding claim , wherein the look up table is arranged to generate the pulse pattern signal at a first rate, and the calculating unit is arranged to select the pulse pattern signal at a second rate, wherein the second rate is at least five times slower than the first rate.
5 . A semiconductor device according to any preceding claim , further comprising: a timer unit connected to the pulse pattern signal output of the coprocessor, the timer unit having: an input connected to the pulse pattern signal output of the coprocessor, and a positive side output and a negative side output for outputting high side and low side pulse pattern signals for driving a half bridge.
6 . A semiconductor device according to claim 5 for driving an inverter for a three phase motor, the inverter having three half bridges, the timer unit comprising three output pairs for driving respective half bridges, each output pair comprising a positive side output and a negative side output.
7 . A semiconductor device according to claim 5 , comprising: three look up tables in parallel, each look up table being for generating a respective PWM signal as a direct function of the generated motor angle, and three pulse pattern signal outputs in parallel for outputting the pulse pattern signal to a respective timer unit.
8 . A semiconductor device according to claim 6 or 7 , wherein the semiconductor device further comprises: a sampling time service request link from the coprocessor to the timer unit; whereby the coprocessor is arranged to generate a plurality of pulse pattern signals, to output the plurality of pulse pattern signals sequentially on the pulse pattern signal output and to output a signal on the sampling time service request link to signal to the timer unit when a pulse pattern output signal is available on the pulse pattern signal output.
9 . A semiconductor device according to claim 8 , wherein the timer unit contains: a sampling unit having an input connected to the pulse pattern output of the coprocessor to sample the pulse pattern signal on the pulse pattern signal output when indicated on the sampling time service request link, and a deadtime and inversion unit comprising an sampling input connected to the output of the sampling unit, further comprising the positive side output unit and the negative side output unit. for each output pair, the deadtime and inversion unit being arranged to generate the high side and low side pulse pattern signals on the positive side output unit and the negative side output unit respectively from the signal on the sampling signal input.
10 . A semiconductor device according to claim 8 or 9 , further comprising a synch service request link from the ADC to the timer unit for signaling the presence of new digitized data captured by the ADC.
11 . A system comprising: a semiconductor device according to any preceding claim ; and at least one half-bridge each containing a high side transistor connected to a positive side output of the semiconductor device and a low side transistor connected to a low side output of the semiconductor device.
12 . A method of generating a pulse pattern signal, comprising: digitizing a signal representing an angle of a motor, determining a motor angle from the digitized signal using an observer; using a look up table to generate a pulse pattern signal as a direct function of the generated motor angle and outputting the pulse pattern signal, and selecting in a calculating unit a look up table based on the determined motor conditions e.g. like acceleration and torque and storing the selected look up table as the look up table.
13 . A method according to claim 12 , further comprising generating a motor speed using the observer and outputting the motor speed to the calculating unit.
14 . A method according to claim 12 or 13 further comprising: generating a high side signal and a low side signal for driving a half bridge form the pulse pattern signal and driving the half bridge with the high side signal and the low side signal.
15 . A method according to claim 12, 13 or 14 for driving an inverter for a three phase motor, the inverter having three half bridges, the method comprising: using three look up tables to generate three respective pulse pattern signals each as a direct function of the generated motor angle and outputting the pulse pattern signals.
16 . A method according to claim 15 , further comprising outputting the plurality of PWM signals sequentially on a pulse pattern signal output and outputting a signal on a sampling time service request link to signal when a pulse pattern output signal is available on the pulse pattern signal output.
17 . A method according to any of claims 12 to 16 , comprising generating the pulse pattern signal at a first rate, and selecting the pulse pattern signal at a second rate, wherein the second rate is at least five times slower than the first rate.

Description

REFERENCE TO RELATED APPLICATION This Application claims priority to German Application number 102024210674.7, filed on Nov. 6, 2024, the contents of which are hereby incorporated by reference in their entirety. FIELD OF THE INVENTION The invention relates to a method of generating a pulse width modulation signal and to a semiconductor device for generating the signal, especially for use in driving a motor. BACKGROUND OF THE INVENTION There is a need to efficiently drive electric motors. For example, in the powertrain of an electric or hybrid vehicle, the electric motor is driven from a battery by a number of drivers. Typically, six power transistors arranged as three half bridges are used to drive a three phase electric motor. The power transistors are driven by signals, typically pulse width modulation signals, i.e. the transistors are either off or on. The power transistors are driven by a driver controlled by a control unit, for example a microcontroller, which generates the signals. One approach is known as space vector pulse width modulation, PWM. When using this approach, a higher switching frequency allows the generation of a PWM signal with reduced ripple and lower harmonic distortion which allows for lower losses in the motor. There is a general need for approaches which avoid excessive losses in motors. SUMMARY OF THE INVENTION According to a first example there is provided a semiconductor device for generating a pulse pattern signal, comprising an analog to digital converter, ADC, for connection to a motor, having an output for indicating the angle of the motor, a coprocessor having an angle input connected to the output of the ADC, an observer connected to the angle input for determining a motor angle, a coprocessor look up table for generating a PWM pulse pattern signal as a direct function of the determined motor angle, and a pulse pattern signal output for outputting the pulse pattern signal, and a calculating unit having an input connected to the coprocessor, the calculating unit being arranged to select a look up table from a plurality of look up tables based on the determined motor conditions e.g. like acceleration and torque and to store the selected look up table as the coprocessor look up table in the coprocessor. By using a look up table in the coprocessor, the example provides a first loop driven directly from the angle measurement; this can deliver a fast loop without requiring complex structures in the semiconductor device. By generating the pulse pattern signal directly from the analog to digital converter, ADC, output the pulse pattern signal can be delivered as fast as the ADC can deliver a signal. Thus the ADC and DSP deliver a fast loop; the updating of the look up table by the calculating unit constitutes a second, slower outer loop. For example, the fast loop can operate on a timeframe of less than 10 μs, for example less than 2 μs, while the outer loop including the calculating unit can operate on a timeframe of more than 20 μs, for example more than 40 μs. This in turn allows the use of a conventional microcontroller general purpose core to deliver the calculations in the outer loop; alternative embodiments may use alternative hardware for example, an alternative core, for example in a parallel processing unit. BRIEF DESCRIPTION OF THE DRAWINGS Examples of the invention will now be described, purely by way of example, with reference to the accompanying drawings, in which: FIG. 1 illustrates an example optimized pulse pattern (A) and an example regular pulse pattern (B). FIG. 2 illustrates example drive signals for a driver together with a driver; FIG. 3 illustrates an example arrangement; FIG. 4 illustrates a further example arrangement. FIG. 5 illustrates example PWM signals; FIG. 6 illustrates example drive signals; FIG. 7 illustrates a further example arrangement; and FIG. 8 illustrates signals corresponding to the arrangement of FIG. 7. DETAILED DESCRIPTION An example of the invention will be presented, purely by way of example. FIG. 1 shows an example of an optimized pulse pattern used to drive a motor (A) and a conventional regular pulse pattern (B). The regular pulse pattern (B) begins pulses at a regular interval and adjusts the length of the pulse to provide pulse width modulation (PWM). Optimized pulse patterns, OPP, can be used to deliver a signal with lower total harmonic distortion, THD, than space vector pulse width modulation. In such optimized patterns, switching is not constrained to be at regular intervals but at times chosen for lower THD and losses. For example, an OPP using a switching frequency of 9 kHz may be able to deliver a THD of 2.3%. In contrast, a SVPWM approach with the same switching frequency of 9 kHz may deliver a current signal with a THD of 5.7%. In order for the SVPWM approach to reach a similar THD, 2.35%, the switching frequency needs to be increased to 20 kHz. This higher switching frequency means that the transistors in the half bri