US-20260128712-A1 - SWITCHABLE ACTIVE ELEMENT FOR INDUCTOR-CAPACITOR (LC) VOLTAGE CONTROLLED OSCILLATOR

Abstract

An apparatus, comprising: a first upper voltage rail; a lower voltage rail; a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal; and a tank circuit coupled to the set of VCO active cores.

Inventors

• Burcin Serter Ergun
• Jose Luis Sanchez
• Sajin Mohamad
• Zhiqin Chen
• Ashwith Jerome REGO

Assignees

• QUALCOMM INCORPORATED

Dates

Publication Date

20260507

Application Date

20241105

Claims (20)

1. 1 . An apparatus, comprising: a first upper voltage rail; a lower voltage rail; a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal; a tank circuit coupled to the set of VCO active cores; and a control circuit, including a differential difference amplifier configured to generate a calibration signal based on a first difference between first and second voltages at respective ports of the tank circuit, and a second difference between first and second reference voltages; and a calibration engine configured to generate the control signal based on the calibration signal.
2. 2 . The apparatus of claim 1 , further comprising a control circuit configured to generate the control signal.
3. 3 . The apparatus of claim 2 , further comprising a first set of switching devices coupled between the first upper voltage rail and the set of VCO active cores, respectively, wherein the control circuit is coupled to the first set of switching devices.
4. 4 . The apparatus of claim 3 , wherein the first set of switching devices comprise at least one set of single pole double throw (SPDT) switching devices including enable terminals coupled to the first upper voltage rail, disable terminals coupled to ground, and pole terminals coupled to the set of VCO active cores, respectively.
5. 5 . The apparatus of claim 2 , further comprising a second set of switching devices coupled between the set of VCO active cores and the lower voltage rail, respectively, and wherein the control circuit is coupled to the second set of switching devices.
6. 6 . The apparatus of claim 5 , wherein the second set of switching devices comprise at least one set of single pole double throw (SPDT) switching devices including enable terminals coupled to the lower voltage rail, disable terminals coupled to ground, and pole terminals coupled to the set of VCO active cores, respectively.
7. 7 . The apparatus of claim 1 , further comprising a low dropout (LDO) voltage regulator coupled between a second upper voltage rail and the first upper voltage rail, wherein the LDO voltage regulator is configured to receive a reference voltage for controlling a supply voltage at the first upper voltage rail.
8. 8 . The apparatus of claim 7 , further comprising a control circuit configured to control the reference voltage.
9. 9 . The apparatus of claim 1 , wherein the tank circuit comprises an inductor-capacitor (LC) tank circuit.
10. 10 . The apparatus of claim 1 , wherein each of the set of VCO active cores comprises cross-coupled field effect transistors (FETs) including drains coupled to first and second ports of the tank circuit, respectively.
11. 11 . The apparatus of claim 10 , wherein the cross-coupled FETs each comprises an n-channel field effect transistor (FET).
12. 12 . The apparatus of claim 1 , wherein each of the set of VCO active cores comprises cross-coupled inverters including outputs coupled to first and second ports of the tank circuit, respectively.
13. 13 . (canceled)
14. 14 . The apparatus of claim 1 , further comprising a low dropout (LDO) voltage regulator coupled between a second upper voltage rail and the first upper voltage rail, wherein the LDO voltage regulator is configured to receive a reference voltage for controlling a supply voltage at the first upper voltage rail, and wherein the calibration engine is configured to control the reference voltage based on the calibration signal.
15. 15 . The apparatus of claim 1 , wherein the tank circuit is configured to receive a frequency control signal in accordance with an operation of a phase locked loop (PLL).
16. 16 . A method, comprising: operating a first set of switching devices to selectively couple one or more of a set of voltage controlled oscillator (VCO) active cores to a first upper voltage rail based on a configuration parameter, wherein the set of VCO active cores are coupled to a tank circuit; and setting a reference voltage applied to a low dropout (LDO) voltage regulator based on the configuration parameter, the LDO voltage regulator coupled between a second upper voltage rail and the first upper voltage rail, wherein the configuration parameter is based on a first difference between first and second voltages at respective ports of the tank circuit, and a second difference between first and second reference voltages.
17. 17 . The method of claim 16 , wherein the configuration parameter is based on a power consumption of the set of VCO active cores.
18. 18 . The method of claim 16 , wherein the configuration parameter is based on a noise in a supply voltage at the first upper voltage rail.
19. 19 . (canceled)
20. 20 . The method of claim 16 , further comprising generating a clock signal at a port of the tank circuit based on a frequency control voltage applied to the tank circuit.

Description

FIELD This disclosure relates generally to oscillators, and in particular, to a voltage controlled oscillator (VCO) including a set of selectively activated VCO active cores for setting power consumption and supply noise characteristics. BACKGROUND A voltage controlled oscillator (VCO) is configured to generate a clock signal for many different purposes. The phase noise of the clock signal may be adversely affected by noise present on the supply voltage provided to the VCO. Further, the VCO also consumes power based on the supply voltage. The supply noise and power consumption of a VCO may also be affected based on process variation of the particular integrated circuit (IC) chip received post-silicon. Lower VCO power consumption and lower supply voltage noise for post-silicon IC chips may be desirable. SUMMARY The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is intended to neither identify key or critical elements of all implementations nor delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later. An aspect of the disclosure relates to an apparatus. The apparatus includes: a first upper voltage rail; a lower voltage rail; a set of voltage controlled oscillator (VCO) active cores, wherein one or more of the set of VCO active cores is selectively coupled to the first upper voltage rail based on a control signal, wherein the set of the VCO active cores are coupled to the lower voltage rail or the one or more of the set of VCO active cores is selectively coupled to the lower voltage rail based on the control signal; a tank circuit coupled to the set of VCO active cores. Another aspect of the disclosure relates to a method. The method includes: operating a first set of switching devices to selectively couple one or more of a set of voltage controlled oscillator (VCO) active cores to a first upper voltage rail based on a configuration parameter, wherein the set of VCO active cores are coupled to a tank circuit; and setting a reference voltage applied to a low dropout (LDO) voltage regulator based on the configuration parameter, the LDO voltage regulator coupled between a second upper voltage rail and the first upper voltage rail. To the accomplishment of the foregoing and related ends, the one or more implementations include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of various implementations may be employed and the description implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a block diagram of an example serializer/deserializer (SERDES) data communication system in accordance with an aspect of the disclosure. FIG. 2 illustrates a block diagram of an example phase locked loop (PLL) in accordance with another aspect of the disclosure. FIG. 3 illustrates a block diagram of an example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 4A illustrates a graph of an example relationship between a current versus active device size associated with the VCO of FIG. 3 in accordance with another aspect of the disclosure. FIG. 4B illustrates a graph of an example relationship between a current versus VCO supply voltage VCCA associated with the VCO of FIG. 3 in accordance with another aspect of the disclosure. FIG. 4C illustrates a graph of an example relationship between attenuation of noise present on the VCO supply voltage VCCA versus the frequency of the supply noise associated with the VCO of FIG. 3 in accordance with another aspect of the disclosure. FIG. 5A illustrates a block diagram of another example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 5B illustrates a block diagram of another example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 6A illustrates a block diagram of another example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 6B illustrates a block diagram of another example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 7 illustrates a block diagram of another example voltage controlled oscillator (VCO) in accordance with another aspect of the disclosure. FIG. 8 illustrates a block diagram of an example apparatus (e.g., a voltage controlled oscillator (VCO)) in accordance with another aspect of t