US-20260128716-A1 - POWER AMPLIFIER WITH STACKED STRUCTURE AND COMMUNICATION CIRCUIT THEREOF

Abstract

A power amplifier is provided. The power amplifier includes: an amplifier circuit including a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and a ground; and a bias circuit including a first operational amplifier configured to provide a first bias voltage to the first transistor, and a second operational amplifier configured to provide a second bias voltage to the second transistor. The first operational amplifier includes a positive input terminal connected to a first reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal.

Inventors

• JooSeok LEE
• Dongsoo Lee
• Daehoon KWON
• Sunggi Yang

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260507

Application Date

20251027

Priority Date

20241106

Claims (20)

1. 1 . A power amplifier comprising: an amplifier circuit comprising a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and a ground; and a bias circuit comprising a first operational amplifier configured to provide a first bias voltage to the first transistor, and a second operational amplifier configured to provide a second bias voltage to the second transistor, wherein the first operational amplifier comprises a positive input terminal connected to a first reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal, and wherein the second operational amplifier comprises a positive input terminal connected to a second reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the second transistor, an output terminal configured to provide the second bias voltage to a gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to the ground.
2. 2 . The power amplifier of claim 1 , further comprising a resistor ladder comprising a first resistor, a second resistor, and a third resistor connected in series between the power supply voltage and the ground, wherein the positive input terminal of the first operational amplifier is connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier is connected to the resistor ladder between the second resistor and the third resistor.
3. 3 . The power amplifier of claim 2 , wherein at least one of the first resistor, the second resistor, or the third resistor is a variable resistor.
4. 4 . The power amplifier of claim 1 , wherein an input radio frequency (RF) signal is received through a gate node of the third transistor, and wherein an amplified output RF signal corresponding to the input RF signal is output through a drain node of the first transistor.
5. 5 . The power amplifier of claim 4 , further comprising an inductor coil connected between the power supply voltage and the drain node of the first transistor.
6. 6 . The power amplifier of claim 1 , wherein the amplifier circuit further comprises a fourth transistor connected to the first transistor in a stacked cascode structure, and wherein the bias circuit further comprises a third operational amplifier configured to provide a bias voltage to the fourth transistor.
7. 7 . The power amplifier of claim 6 , further comprising a voltage regulator configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier, based on the power supply voltage.
8. 8 . The power amplifier of claim 1 , further comprising an analog bias circuit comprising a mirror transistor corresponding to the third transistor and a third operational amplifier configured to provide a third bias voltage to the mirror transistor, wherein the third operational amplifier comprises a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to the ground, and wherein the mirror transistor comprises a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage via a reference current source, and a source node connected to the ground.
9. 9 . The power amplifier of claim 1 , wherein the first transistor, the second transistor, and the third transistor are complementary metal-oxide-semiconductor (MOS) (CMOS) transistors.
10. 10 . The power amplifier of claim 1 , wherein the amplifier circuit is configured to be used in a transmission path of an RF communication circuit configured to support a millimeter wave (mmWave) frequency band.
11. 11 . A communication circuit including a transmission path, wherein the transmission path comprises one or more power amplifiers, and among the one or more power amplifiers, at least one power amplifier comprises: an amplifier circuit comprising a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and a ground; and a bias circuit comprising a first operational amplifier configured to provide a first bias voltage to the first transistor, and a second operational amplifier configured to provide a second bias voltage the second transistor, wherein the first operational amplifier comprises a positive input terminal connected to a first reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal, and wherein the second operational amplifier comprises a positive input terminal connected to a second reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the second transistor, an output terminal configured to provide the second bias voltage to a gate node of the second transistor, a positive power supply terminal connected to the negative power supply terminal of the first operational amplifier, and a negative power supply terminal connected to the ground.
12. 12 . The communication circuit of claim 11 , wherein the at least one power amplifier further comprises a resistor ladder including a first resistor, a second resistor, and a third resistor connected in series between the power supply voltage and the ground, and wherein the positive input terminal of the first operational amplifier is connected to the resistor ladder between the first resistor and the second resistor, and the positive input terminal of the second operational amplifier is connected to the resistor ladder between the second resistor and the third resistor.
13. 13 . The communication circuit of claim 12 , wherein at least one of the first resistor, the second resistor, or the third resistor is a variable resistor.
14. 14 . The communication circuit of claim 11 , wherein an input radio frequency (RF) signal is received through a gate node of the third transistor, and wherein an amplified output RF signal corresponding to the input RF signal is output through a drain node of the first transistor.
15. 15 . The communication circuit of claim 14 , wherein the amplifier circuit further comprises an inductor coil connected between the power supply voltage and the drain node of the first transistor.
16. 16 . The communication circuit of claim 11 , wherein the amplifier circuit further comprises a fourth transistor connected to the first transistor in a stacked cascode structure, and wherein the bias circuit further comprises a third operational amplifier configured to provide a bias voltage to the fourth transistor.
17. 17 . The communication circuit of claim 16 , wherein the amplifier circuit further comprises a voltage regulator configured to generate source voltages to be provided to the first operational amplifier and the second operational amplifier, based on the power supply voltage.
18. 18 . The communication circuit of claim 11 , wherein the amplifier circuit further comprises an analog bias circuit including a mirror transistor corresponding to the third transistor and a third operational amplifier configured to provide a third bias voltage to the mirror transistor, wherein the third operational amplifier comprises a positive input terminal connected to an analog power supply voltage, a negative input terminal connected to the positive input terminal of the second operational amplifier, a positive power supply terminal connected to the analog power supply voltage, and a negative power supply terminal connected to the ground, and wherein the mirror transistor comprises a gate node connected to the gate node of the third transistor, a drain node connected to the analog power supply voltage via a reference current source, and a source node connected to the ground.
19. 19 . The communication circuit of claim 11 , wherein the first transistor, the second transistor, and the third transistor are complementary metal-oxide-semiconductor (MOS) (CMOS) transistors.
20. 20 . The communication circuit of claim 11 , wherein the transmission path is configured to support a millimeter wave (mmWave) frequency band.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a bypass continuation of International application No. PCT/KR2025/014882, filed on Sep. 23, 2025, which is based on and claims priority to Korean Patent Application No. 10-2024-0156471, filed on Nov. 6, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. BACKGROUND 1. Field One or more embodiments relate to a power amplifier with a stacked structure and a communication circuit thereof. 2. Description of Related Art To meet the growing demand for wireless data traffic following 4G systems (i.e., long-term evolution (LTE) systems), 5G systems are being developed and commercialized. 5G systems may be implemented in a millimeter wave (mmWave) band. To mitigate path loss of radio waves and increase the transmission distance of radio waves in the mmWave band, ongoing research is being performed with respect to beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beamforming, and large-scale antenna. In a MIMO-based 5G system using the mmWave band, a base station may form single beam or multiple beams through array antennas and use the beams for communication with a user equipment (UE). The base station may improve communication quality by concentrating signals in the direction of each of one or more UEs through beamforming. With the advancement of technologies such as the internet of things (IoT), cloud computing, and big data, and the increase in public data consumption, the demand for large-capacity wireless communication technology is rapidly increasing. Frequency bands are becoming saturated with various communication services and have limited bandwidths, making it difficult to provide higher data transmission rates. Therefore, signal processing in higher frequency bands is required to implement large-capacity wireless communication technology. A high frequency band, for example, the mmWave band above 10 GHz, may significantly increase data transmission rates based on a wide bandwidth and avoid congestion in a low frequency band, thereby enabling high-quality communication services to be provided. However, the mmWave band suffers from large propagation loss and is easily blocked by obstacles. In order to overcome the above problems, research on beamforming, increasing a cell density, and high-power power amplifiers is being conducted. A high-power power amplifier amplifies the strength of an output signal to increase a communication distance and provide a stable connection. A complementary metal-oxide-semiconductor (CMOS) field-effect transistor (MOSFET)-based power amplifier is inexpensive and has a very high integration level, which may facilitate implementation of beamforming technology at a high frequency. However, compared to other compound semiconductors (e.g., gallium arsenide (GaAs) or gallium nitride (GaN)), low power may be available for the CMOS-based power amplifier and it may be difficult to provide high output power with the CMOS-based power amplifier. The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure. SUMMARY One or more embodiments provide a power amplifier with a stacked structure and a communication circuit thereof. One or more embodiments also provide a communication circuit including a bias circuit for a stacked cascade power amplifier. The technical problems to be solved by the disclosure is not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the disclosure pertains from the following description. According to embodiments of the disclosure, a power amplifier may include: an amplifier circuit including a first transistor, a second transistor, and a third transistor connected in a stacked cascode structure between a power supply voltage and a ground; and a bias circuit including a first operational amplifier configured to provide a first bias voltage to the first transistor, and a second operational amplifier configured to provide a second bias voltage to the second transistor. The first operational amplifier may include a positive input terminal connected to a first reference voltage divided from the power supply voltage, a negative input terminal connected to a source node of the first transistor, an output terminal configured to provide the first bias voltage to a gate node of the first transistor, a positive power supply terminal connected to the power supply voltage, and a negative power supply terminal. The second operational amplifier may include a positive input terminal connected to a second reference voltage divided from the power supply volta