US-20260128718-A1 - HIGH-VOLTAGE SUPER-CASCODE STRUCTURES WITH SELF-PROTECTION CIRCUITRY

US20260128718A1US 20260128718 A1US20260128718 A1US 20260128718A1US-20260128718-A1

Abstract

A cascode structure may include a switching path comprising a main N-type field effect transistor switching device having a first gate and a cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and having a second gate and a circuit coupled between the first gate and the second gate. The circuit may be configured to in an off-state of the switching path, provide a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main N-type field effect transistor switching device and such that the switching path is able to tolerate as high as the sum of the drain-to-source breakdown voltages of the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device.

Inventors

Arashk NOROUZPOURSHIRAZI
Eric J. King
John L. Melanson

Assignees

CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Dates

Publication Date: 20260507
Application Date: 20250929
Priority Date: 20241120

Claims (20)

1 . A cascode structure comprising: a switching path comprising: a main N-type field effect transistor switching device having a first gate; and a cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and having a second gate; and a circuit coupled between the first gate and the second gate, wherein the circuit is configured to: in an off-state of the switching path, provide a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main N-type field effect transistor switching device and such that the switching path is able to tolerate as high as the sum of the drain-to-source breakdown voltages of the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device; and in an on-state of the switching path, provide a low-impedance path between the first gate and the second gate, such that a first voltage on the first gate and a second voltage on the second gate are approximately equal and the circuit is controlled by a voltage at a drain of the main N-type field effect transistor switching device.
2 . The cascode structure of claim 1 , wherein the circuit comprises a high-voltage P-type field effect transistor.
3 . The cascode structure of claim 1 , wherein the second gate is switched by a switched capacitor or a clocked driver, via the circuit, to a protection voltage for biasing the second gate.
4 . The cascode structure of claim 1 , wherein the protection voltage is generated by a resistive divider.
5 . The cascode structure of claim 4 , wherein the resistive divider is a resistor ladder.
6 . The cascode structure of claim 1 , wherein the second gate is switched to a protection voltage for biasing the second gate by a diode clamp coupled to the second gate, wherein the diode clamp turns on as a drain of the cascode switching N-type field effect transistor device goes high.
7 . The cascode structure of claim 1 , wherein: the switching path further comprises a second cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device and having a third gate; and multiple protection voltages are used to clamp the second gate and the third gate during the off-state.
8 . The cascode structure of claim 1 , wherein: the second gate is controlled by a diode clamp to a protection voltage; and the first gate is coupled to a switching path clock via a delay element such that the main N-type field effect transistor switching device pulls down a source of the cascode switching N-type field effect transistor device during a high-to-low transition of a source terminal of the main N-type transistor.
9 . The cascode structure of claim 8 , wherein the delay element comprises a clocked delay circuit having digital logic and delay cells.
10 . The cascode structure of claim 8 , wherein the delay element comprises a resistor coupled to the first gate.
11 . A cascode structure comprising: a switching path comprising: a main P-type field effect transistor switching device having a first gate; and a cascode switching P-type field effect transistor device in series with the main P-type field effect transistor switching device and having a second gate; and a circuit coupled between the first gate and the second gate, wherein the circuit is configured to: in an off-state of the switching path, provide a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main P-type field effect transistor switching device and such that the switching path is able to tolerate as high as the sum of the drain-to-source breakdown voltages of the main P-type field effect transistor switching device and the cascode switching P-type field effect transistor device; and in an on-state of the switching path, provide a low-impedance path between the first gate and the second gate, such that a first voltage on the first gate and a second voltage on the second gate are approximately equal and the circuit is controlled by a voltage at a drain of the main P-type field effect transistor switching device.
12 . The cascode structure of claim 11 , wherein the circuit comprises a high-voltage N-type field effect transistor.
13 . The cascode structure of claim 11 , wherein the second gate is switched by a switched capacitor or a clocked driver, via the circuit, to a protection voltage for biasing the second gate.
14 . The cascode structure of claim 11 , wherein the protection voltage is generated by a resistive divider.
15 . The cascode structure of claim 14 , wherein the resistive divider is a resistor ladder.
16 . The cascode structure of claim 11 , wherein the second gate is switched to a protection voltage for biasing the second gate by a diode clamp coupled to the second gate, wherein the diode clamp turns on as a drain of the cascode switching N-type field effect transistor device goes high.
17 . The cascode structure of claim 11 , wherein: the switching path further comprises a second cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device and having a third gate; and multiple protection voltages are used to clamp the second gate and the third gate during the off-state.
18 . A method in a cascode structure having a switching path comprising a main N-type field effect transistor switching device having a first gate and a cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and having a second gate, the method comprising, with a circuit coupled between the first gate and the second gate: in an off-state of the switching path, providing a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main N-type field effect transistor switching device and such that the switching path is able to tolerate as high as the sum of the drain-to-source breakdown voltages of the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device; and in an on-state of the switching path, providing a low-impedance path between the first gate and the second gate, such that a first voltage on the first gate and a second voltage on the second gate are approximately equal and the circuit is controlled by a voltage at a drain of the main N-type field effect transistor switching device.
19 . The method of claim 18 , wherein the circuit comprises a high-voltage P-type field effect transistor.
20 . The method of claim 18 , further comprising switching the second gate by a switched capacitor or a clocked driver, via the circuit, to a protection voltage for biasing the second gate.

Description

RELATED APPLICATIONS The present disclosure claims priority to U.S. Provisional Patent Application Ser. No. 63/716,543, filed Nov. 5, 2024, and United Kingdom Patent Application No. 2417069.8, filed Nov. 20, 2024, each of which is incorporated by reference herein in its entirety. FIELD OF DISCLOSURE The present disclosure relates in general to charge pumps, including without limitation those used in personal audio devices such as wireless telephones and media players, and more specifically, to high-voltage cascode structures having self-protection circuitry which are used in charge pumps. BACKGROUND Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers, and the power amplifier may often be the primary consumer of power in a personal audio device, and thus, may have the greatest effect on the battery life of the personal audio device. In devices having a linear power amplifier for the output stage, power is wasted during low signal level outputs, because the voltage drop across the active output transistor plus the output voltage will be equal to the constant power supply rail voltage. Therefore, amplifier topologies such as Class-G and Class-H are desirable for reducing the voltage drop across the output transistor(s) and thereby reducing the power wasted in dissipation by the output transistor(s). In order to provide a variable power supply voltage to such a power amplifier, a charge pump power supply may be used, for example such as that disclosed in U.S. Pat. No. 8,311,243, in which an indication of the signal level at the output of the circuit is used to control the power supply voltage in a Class-G topology. The above-described topology may raise the efficiency of the audio amplifier, in general, as long as periods of low signal level are present in the audio source. Typically in such topologies, a plurality of thresholds define output signal level-dependent operating modes for the charge pump power supply, wherein a different supply voltage is generated by the charge pump power supply in each mode. In a typical switching charge pump, metal-oxide semiconductor field-effect transistors (MOSFETs) used to implement switches may have breakdown voltages that limit the amount of power that may be transferred through the MOSFETs. Accordingly, charge pumps for structures that mitigate the limitations of transistor breakdown voltages may be desired. SUMMARY In accordance with the teachings of the present disclosure, certain disadvantages and problems associated with performance of charge pumps have been reduced or eliminated. In accordance with embodiments of the present disclosure, a cascode structure may include a switching path comprising a main N-type field effect transistor switching device having a first gate and a cascode switching N-type field effect transistor device in series with the main N-type field effect transistor switching device and having a second gate and a circuit coupled between the first gate and the second gate. The circuit may be configured to in an off-state of the switching path, provide a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main N-type field effect transistor switching device and such that the switching path is able to tolerate as high as the sum of the drain-to-source breakdown voltages of the main N-type field effect transistor switching device and the cascode switching N-type field effect transistor device. The circuit may also be configured to in an on-state of the switching path, provide a low-impedance path between the first gate and the second gate, such that a first voltage on the first gate and a second voltage on the second gate are approximately equal and the circuit is controlled by a voltage at a drain of the main N-type field effect transistor switching device. In accordance with these and other embodiments of the present disclosure, a cascode structure may include a switching path comprising a main P-type field effect transistor switching device having a first gate and a cascode switching P-type field effect transistor device in series with the main P-type field effect transistor switching device and having a second gate and a circuit coupled between the first gate and the second gate. The circuit may be configured to in an off-state of the switching path, provide a high-impedance path between the first gate and the second gate, such that the second gate is switched to a protection voltage as high as a drain-to-source breakdown voltage of the main P-type field effect transistor switching d