US-20260128720-A1 - Circuitry for and Methods of Gain Control

US20260128720A1US 20260128720 A1US20260128720 A1US 20260128720A1US-20260128720-A1

Abstract

An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.

Inventors

Andrew J. HOWLETT
Michael CHANDLER-PAGE
David P. Singleton
Erich P. ZWYSSIG

Assignees

CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Dates

Publication Date: 20260507
Application Date: 20251219

Claims (20)

1 . An integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal to generate a first amplified output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage.
2 . The IC of claim 1 , wherein the gain update circuitry is further configured to: monitor the first input signal or the first output signal for a signal event at which to update the first gain of the first gain stage; and time-align output of the first internal gain control signal to temporally coincide with the signal event reaching the first gain stage.
3 . The IC of claim 2 , wherein the signal event comprises a zero-crossing of the first input signal or the first output signal, wherein the gain update circuitry comprises zero-cross detection circuitry configured to monitor the first input signal or the first output signal for the zero-crossing.
4 . The IC of claim 1 , wherein the gain update circuitry is configured to: receive a first signal event flag at a signal event input pin of the IC; and time output of the internal gain control signal based on a time at which the signal event flag is received.
5 . The IC of claim 4 , wherein the first signal event flag signifies a zero-crossing in the first input signal.
6 . The IC of claim 4 , wherein the gain updated circuitry comprises level detection circuitry configured to process the received first signal event flag.
7 .- 8 . (canceled)
9 . The IC of claim 1 , further comprising filter circuitry provided between the first input pin and the converter, the filter circuitry configured to filter the first input signal to be provided to the converter, wherein the filter circuitry contributes to the signal chain delay.
10 .- 12 . (canceled)
13 . The IC of claim 1 , further comprising: an interface for receiving first gain settings from a host device; one or more registers for storing the first gain settings, wherein the gain update circuitry is configured to: read the first gain settings from the one or more registers; and generate the first external gain control signal and/or the first internal gain control signal based on the first gain settings.
14 . The IC of claim 13 , wherein the first gain setting comprise a first external gain setting and a first internal gain setting, wherein the first internal and first external gain settings are stored in separate ones of the one or more registers, and wherein the first external and internal gain settings are treated atomically by the gain control circuitry.
15 . (canceled)
16 . The IC of claim 13 , wherein the gain update circuitry is configured to: determine whether the first gain setting is within a dynamic range of the first gain of the first gain stage; if the first gain setting is within the dynamic range of the first gain of the first gain stage, update the first internal gain control signal based on the first gain setting; if the first gain setting is outside the dynamic range of the first gain of the first gain stage, update the first internal gain control signal and the first external gain control signal.
17 . (canceled)
18 . The IC of claim 1 , further comprising: a second input pin for receiving a second input signal; a second converter configured to convert the second input signal to a second output signal; a second gain stage configured to apply a second gain to the second output signal; wherein the gain update circuitry is configured to: output a second external gain control signal to a second output pin of the IC; and subsequently output a second internal gain control signal to the second gain stage to update the second gain of the second gain stage, wherein output of the second internal gain control signal is delayed relative to output of the second external gain control signal by a second predetermined delay, the second predetermined delay to compensate for signal chain delay between the second input pin and the second gain stage.
19 . A system comprising: a first analog input for receiving a first analog input signal; a first analog gain stage configured to apply a first analog gain to the first analog input signal to generate the first input signal; and the IC of claim 1 .
20 . (canceled)
21 . The system of claim 19 , wherein the first analog gain stage comprises a zero-crossing detector configured to detect a zero-crossing event in the analog input signal.
22 . (canceled)
23 . The system of claim 19 , further comprising external filter circuitry provided between the first analog gain stage and the IC, the external filter circuitry configured to filter the first input signal to be provided to the IC, wherein the filter circuitry contributes to the signal chain delay.

Description

TECHNICAL FIELD The present disclosure relates to an apparatus, systems and methods of gain control. BACKGROUND Gain control circuits are widely-used to vary the gain of signals from various sources. Such gain control circuits may be implemented as part of a signal chain which may include a converter, such as an analog-to-digital converter (ADC), to convert an analog input signal to a digital output signal. Such an implementation can be found, for example, in a typical audio mixing desk, to control the volume level of a signal received from an analog source (e.g., a microphone or other line-in port). Traditionally, gain control is implemented using an analog potentiometer to continuously vary a resistance in the signal chain to adjust the signal level of the output signal. An analog potentiometer cannot easily be controlled by digital means and therefore cannot easily be integrated into a digital audio processing system (such as a digital mixing console). Where digital control of gain is required, a combination of discrete resistors and switches may be implemented to adjust the resistance of a signal chain in low-resolution step changes based on digital control of the switches. Such gain control is typically combined with fine-resolution gain control in a digital audio processing system, which is used to allow fine tuning of gain between each of the low-resolution steps. A challenge in such systems is the ability to synchronise updates in the low- and high-resolution gain applied to an input signal. SUMMARY According to a first aspect of the disclosure, there an integrated circuit (IC), comprising: a first input pin for receiving a first input signal; a first converter configured to convert the first input signal to a first output signal; a first gain stage configured to apply a first gain to the first output signal to generate a first amplified output signal; gain update circuitry configured to: output a first external gain control signal to a first output pin of the IC; and subsequently output a first internal gain control signal to the first gain stage to update the first gain of the first gain stage, wherein output of the first internal gain control signal is delayed relative to output of the first external gain control signal by a first predetermined delay, the first predetermined delay to compensate for signal chain delay between the first input pin and the first gain stage. The gain update circuitry may be further configured to: monitor the first input signal or the first output signal for a signal event at which to update the first gain of the first gain stage; and time-align output of the first internal gain control signal to temporally coincide with the signal event reaching the first gain stage. The signal event may comprise a zero-crossing of the first input signal or the first output signal. The gain update circuitry may comprise zero-cross detection circuitry configured to monitor the first input signal or the first output signal for the zero-crossing. The gain update circuitry is configured to: receive a first signal event flag at a signal event input pin of the IC; and time output of the internal gain control signal based on a time at which the signal event flag is received. The first signal event flag may signify a zero-crossing in the first input signal. The gain updated circuitry may comprise level detection circuitry configured to process the received first signal event flag. The level detection circuitry may comprise a flash analog-to-digital converter (ADC). The converter may comprise an analog-to-digital converter. The IC may further comprise filter circuitry provided between the first input pin and the converter, the filter circuitry configured to filter the first input signal to be provided to the converter. The filter circuitry may contribute to the signal chain delay. The filter circuitry may be configured to low-pass filter the first input signal. The filter circuitry may be configured to impedance match the first input signal to an input impedance of the converter. The first input signal may be an audio signal. The IC may further comprise an interface for receiving first gain settings from a host device; one or more registers for storing the first gain settings. The gain update circuitry may be configured to: read the first gain settings from the one or more registers; and generate the first external gain control signal and/or the first internal gain control signal based on the first gain settings. The first gain setting may comprise a first external gain setting and a first internal gain setting. The first internal and first external gain settings may be stored in separate ones of the one or more registers. The first external and internal gain settings may be treated atomically by the gain control circuitry. For example, the gain control circuitry may be configured to copy or read the first external and internal gain settings if an update flag in the one or more registers is fl