US-20260128732-A1 - MULTIPLEXER CIRCUIT FOR A BATTERY MANAGEMENT SYSTEM, AND CORRESPONDING BATTERY MANAGEMENT SYSTEM

US20260128732A1US 20260128732 A1US20260128732 A1US 20260128732A1US-20260128732-A1

Abstract

A MUX for a battery management system includes first, second, and third input terminals for coupling to first, second, and third pins of a battery stack, respectively. First, second, and third switches have respective first, second, and third terminals coupled to the first, second, and third input terminals of the MUX, respectively. An AFE and selection circuit includes first, second, and third input terminals coupled to second terminals of the first, second, and third switches, respectively, first and third output terminals for coupling to positive inputs of first and second shifter circuits, second and fourth output terminals for coupling to negative inputs of the first and second level shifter circuits, respectively. Each of the first, second, third and fourth output terminals of the AFE and selection circuit is selectively couplable to any of the first, second and third input terminals of the AFE and selection circuit.

Inventors

Carlo CURINA
Valerio Bendotti
Alice Marzioli

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260507
Application Date: 20251013
Priority Date: 20241107

Claims (20)

1 . A multiplexer circuit (MUX) for a battery management system, the MUX comprising: a first input terminal configured to couple to a first pin of a battery stack, a second input terminal configured to couple to a second pin of the battery stack, and a third input terminal configured to couple to a third pin of the battery stack; a first switch having a respective first terminal coupled to the first input terminal of the MUX, a second switch having a respective first terminal coupled to the second input terminal of the MUX, and a third switch having a respective first terminal coupled to the third input terminal of the MUX; and an analog front end (AFE) and selection circuit comprising: a first input terminal coupled to a second terminal of the first switch; a second input terminal coupled to a second terminal of the second switch; a third input terminal coupled to a second terminal of the third switch; a first output terminal configured to couple to a positive input of a first level shifter circuit; a second output terminal configured to couple to a negative input of the first level shifter circuit; a third output terminal configured to couple to a positive input of a second level shifter circuit; and a fourth output terminal configured to couple to a negative input of the second level shifter circuit; wherein each of the first, second, third, and fourth output terminals of the AFE and selection circuit is selectively couplable to any of the first, second, and third input terminals of the AFE and selection circuit.
2 . The multiplexer circuit of claim 1 , wherein the AFE and selection circuit comprises: a first 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the first output terminal of the AFE and selection circuit; a second 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the second output terminal of the AFE and selection circuit; a third 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the third output terminal of the AFE and selection circuit; and a fourth 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the fourth output terminal of the AFE and selection circuit.
3 . The multiplexer circuit of claim 1 , wherein the AFE and selection circuit comprises a first selector, a second selector, a third selector and a fourth selector, wherein each of the selectors has respective first and second inputs and respective first and second outputs, wherein any output of each selector is selectively couplable to any input of the same selector, and wherein: the first input of the first selector is connected to the first input terminal of the AFE and selection circuit; the second input of the first selector is connected to the second input terminal of the AFE and selection circuit; the first input of the second selector is connected to the second input terminal of the AFE and selection circuit; the second input of the second selector is connected to the third input terminal of the AFE and selection circuit; the first input of the third selector is connected to the first output of the first selector; the second input of the third selector is connected to the first output of the second selector; the first input of the fourth selector is connected to the second output of the first selector; the second input of the fourth selector is connected to the second output of the second selector; the first output of the third selector is connected to the positive input of the first level shifter circuit; the second output of the third selector is connected to the negative input of the first level shifter circuit; the first output of the fourth selector is connected to the positive input of the second level shifter circuit; and the second output of the fourth selector is connected to the negative input of the second level shifter circuit.
4 . The multiplexer circuit of claim 1 , wherein each of the first, second and third switches comprises a first transistor and a second transistor having respective conductive channels arranged in series between an input terminal and an output terminal of the switch.
5 . The multiplexer circuit of claim 4 , wherein in each of the first, second and third switches, the first transistor includes an n-channel metal-oxide-semiconductor (MOS) transistor having a drain terminal coupled to the input terminal of the switch, a source terminal coupled to a common node, and a gate terminal coupled to a selection node, and the second transistor includes an n-channel MOS transistor having a drain terminal coupled to the output terminal of the switch, a source terminal coupled to the common node, and a gate terminal coupled to the selection node.
6 . The multiplexer circuit of claim 5 , wherein each of the first, second and third switches comprises: a current source coupled between a power supply rail and the selection node, and configured to source a current to the selection node; and a resistor and a third transistor arranged in series between the selection node and ground.
7 . The multiplexer circuit of claim 6 , wherein in each of the first, second and third switches, the third transistor comprises a p-channel MOS transistor having a drain terminal coupled to ground, a source terminal coupled to the respective resistor, and a gate terminal coupled to the common node.
8 . The multiplexer circuit of claim 5 , wherein each of the first, second and third switches comprises a diode having an anode terminal coupled to the selection node and a cathode terminal coupled to a biasing node.
9 . The multiplexer circuit of claim 3 , wherein each of the first and second selectors comprises: a current source coupled between a power supply rail and a biasing node, and configured to source a first current to the biasing node; a Zener diode having an anode terminal coupled to a further biasing node and a cathode terminal coupled to the biasing node; a fourth transistor and a fifth transistor having respective conductive channels arranged in parallel between the further biasing node and a floating ground node, wherein a control terminal of the fourth transistor is connected to a first input node of the selector and a control terminal of the fifth transistor is connected to a second input node of the selector; and a further current source coupled between the floating ground node and ground, and configured to sink a second current from the floating ground node.
10 . The multiplexer circuit of claim 9 , wherein each of the first and second selectors comprises a passgate circuit block coupled between the two inputs of the selector and the two outputs of the selector, and comprising one or more CMOS passgate circuits to selectively couple any output of the selector to any input of the selector.
11 . The multiplexer circuit of claim 10 , wherein each of the first and second selectors comprises: a sixth transistor having a conductive channel arranged between the power supply rail and a secondary supply node and a control terminal coupled to the biasing node; and a second Zener diode having an anode terminal coupled to the floating ground node and a cathode terminal coupled to the secondary supply node; wherein the passgate circuit block is biased between the secondary supply node and the floating ground node.
12 . The multiplexer circuit of claim 1 , comprising: a fourth input terminal configured to couple to ground, and a fifth input terminal configured to couple to a general-purpose input pin; and a fourth switch having a respective first terminal coupled to the fourth input terminal of the MUX, and a fifth switch having a respective first terminal coupled to the fifth input terminal of the MUX; wherein the first input terminal of the AFE and selection circuit is coupled to a second terminal of the fourth switch and the second input terminal of the AFE and selection circuit is coupled to a second terminal of the fifth switch.
13 . The multiplexer circuit of claim 1 , comprising: a sixth input terminal configured to couple to a reference pin; and a sixth switch having a respective first terminal coupled to the sixth input terminal of the MUX; wherein the second input terminal of the AFE and selection circuit is coupled to a second terminal of the sixth switch.
14 . A battery management system comprising: a multiplexer circuit (MUX) comprising: a first input terminal configured to couple to a first pin of a battery stack, a second input terminal configured to couple to a second pin of the battery stack, and a third input terminal configured to couple to a third pin of the battery stack; a first switch having a respective first terminal coupled to the first input terminal of the MUX, a second switch having a respective first terminal coupled to the second input terminal of the MUX, and a third switch having a respective first terminal coupled to the third input terminal of the MUX; and an analog front end (AFE) and selection circuit comprising: a first input terminal coupled to a second terminal of the first switch; a second input terminal coupled to a second terminal of the second switch; a third input terminal coupled to a second terminal of the third switch; a first output terminal configured to couple to a positive input of a first level shifter circuit; a second output terminal configured to couple to a negative input of the first level shifter circuit; a third output terminal configured to couple to a positive input of a second level shifter circuit; and a fourth output terminal configured to couple to a negative input of the second level shifter circuit; wherein each of the first, second, third, and fourth output terminals of the AFE and selection circuit is selectively couplable to any of the first, second, and third input terminals of the AFE and selection circuit; a first level shifter circuit having a positive input coupled to the first output terminal of the AFE and selection circuit, a negative input coupled to the second output terminal of the AFE and selection circuit, and an output port; a second level shifter circuit having a positive input coupled to the third output terminal of the AFE and selection circuit, a negative input coupled to the fourth output terminal of the AFE and selection circuit, and an output port; a first analog-to-digital converter (ADC) circuit having an input port coupled to the output port of the first level shifter circuit; and a second ADC circuit having an input port coupled to the output port of the second level shifter circuit.
15 . The battery management system of claim 14 , wherein the third pin of the battery stack is connected to an anode terminal of an odd-numbered cell of the battery stack, the second pin of the battery stack is connected to a cathode terminal of the odd-numbered cell of the battery stack and to an anode terminal of a subsequent even-numbered cell of the battery stack, and the first pin of the battery stack is connected to a cathode terminal of the subsequent even-numbered cell of the battery stack.
16 . The battery management system of claim 14 , wherein the AFE and selection circuit comprises: a first 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the first output terminal of the AFE and selection circuit; a second 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the second output terminal of the AFE and selection circuit; a third 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the third output terminal of the AFE and selection circuit; and a fourth 4:1 MUX having three inputs respectively coupled to the first, second and third input terminal of the AFE and selection circuit and having one output coupled to the fourth output terminal of the AFE and selection circuit.
17 . The battery management system of claim 14 , wherein the AFE and selection circuit comprises a first selector, a second selector, a third selector and a fourth selector, wherein each of the selectors has respective first and second inputs and respective first and second outputs, wherein any output of each selector is selectively couplable to any input of the same selector, and wherein: the first input of the first selector is connected to the first input terminal of the AFE and selection circuit; the second input of the first selector is connected to the second input terminal of the AFE and selection circuit; the first input of the second selector is connected to the second input terminal of the AFE and selection circuit; the second input of the second selector is connected to the third input terminal of the AFE and selection circuit; the first input of the third selector is connected to the first output of the first selector; the second input of the third selector is connected to the first output of the second selector; the first input of the fourth selector is connected to the second output of the first selector; the second input of the fourth selector is connected to the second output of the second selector; the first output of the third selector is connected to the positive input of the first level shifter circuit; the second output of the third selector is connected to the negative input of the first level shifter circuit; the first output of the fourth selector is connected to the positive input of the second level shifter circuit; and the second output of the fourth selector is connected to the negative input of the second level shifter circuit.
18 . The battery management system of claim 14 , wherein each of the first, second and third switches comprises a first transistor and a second transistor having respective conductive channels arranged in series between an input terminal and an output terminal of the switch.
19 . The battery management system of claim 14 , wherein the MUX comprises: a fourth input terminal configured to couple to ground, and a fifth input terminal configured to couple to a general-purpose input pin; and a fourth switch having a respective first terminal coupled to the fourth input terminal of the MUX, and a fifth switch having a respective first terminal coupled to the fifth input terminal of the MUX; wherein the first input terminal of the AFE and selection circuit is coupled to a second terminal of the fourth switch and the second input terminal of the AFE and selection circuit is coupled to a second terminal of the fifth switch.
20 . The battery management system of claim 14 , wherein the MUX comprises: a sixth input terminal configured to couple to a reference pin; and a sixth switch having a respective first terminal coupled to the sixth input terminal of the MUX; wherein the second input terminal of the AFE and selection circuit is coupled to a second terminal of the sixth switch.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Italian Patent Application No. 102024000025068, filed on November 7, 2024, which application is hereby incorporated herein by reference. TECHNICAL FIELD The description relates to multiplexer circuits (MUX) that can be used in battery management systems (BMS), in particular for coupling the pins of a stack of battery cells to the input terminals of a set of analog-to-digital converters (ADC) of the BMS. BACKGROUND A battery management system is an electronic device or system configured to monitor and/or control a rechargeable battery. For instance, a BMS can be configured to control the battery so that it does not operate outside its safe operating area (SOA), and/or to monitor the state of the battery by running some diagnosis procedures. Batteries couplable to a BMS can include, for instance, high-voltage (e.g., 400 V or 800 V) battery packs for battery electric vehicles (BEV) or hybrid electric vehicles (HEV and PHEV), mild-voltage (e.g., 48 V) battery packs for mild-hybrid electric vehicles (MHEV), batteries for backup energy storage systems and uninterruptible power supplies (UPS), and the like. A function of a BMS device is that of measuring the voltage of each battery cell inside the stack of cells (i.e., a plurality of cells connected in series) of a battery or battery pack, in order to be able to carry out some internal functions such as charge balancing, diagnosis, temperature sensing, and others. Usually, due to timing requirements, each of the n cells of the stack has to be selectively connectable to a dedicated ADC circuit. In this respect, reference may be made to FIG. 1, which is a circuit block diagram exemplary of a possible arrangement of a battery B coupled to a BMS 10. The battery B includes a stack of n battery cells coupled in series, from a “lowest” (or first) cell Cell1 to a “highest” (or nth) cell Celln. The first cell Cell1 has its anode terminal coupled to ground GND and its cathode terminal coupled to the anode terminal of the second cell Cell2, each intermediate cell (from Cell2 to Celln-1) has its anode terminal coupled to the cathode terminal of a previous cell and its cathode terminal coupled to the anode terminal of a next cell, and the last cell Celln has its anode terminal coupled to the cathode terminal of the previous cell Celln-1 and its cathode terminal coupled to a topmost pin of the battery stack, which provides the maximum output voltage of the battery stack. The battery stack has n+1 pins, including a pin C0 coupled to ground, and pins C1 to Cn each coupled to the cathode terminal of the respective cell (i.e., Cell1 to Celln). The BMS 10 includes an analog multiplexer circuit 12 having n+1 input terminals, each coupled to a respective one of the pins C0 to Cn of the battery stack, and n pairs of output terminals, each pair being coupled to the input port of a respective ADC circuit 14. The ADC circuits 141 to 14n produce respective digital output signals (e.g., multi-bit signals) bs 1 to bsn. Due to the typical voltage ratings of the battery B, the MUX 12 may be designed to withstand an absolute maximum voltage of about 100 V pin-to-pin and pin-to-ground. In order to better understand the connections that can be implemented by the MUX 12, reference can be made to FIG. 2, which is a circuit block diagram showing in detail the architecture of the MUX 12 that is implemented for connecting the pins of two consecutive cells, a generic odd-numbered cell Celli-1 and a generic even-numbered cell Celli, to the respective ADCs 14i-1 and 14i. It will be understood that the architecture of FIG. 2 may be replicated, in the MUX 12, for each pair of consecutive battery cells (each pair comprising an odd-numbered cell and an even-numbered cell, e.g., Cell1 and Cell2, Cell3 and Cell4, up to Celln-1 and Celln). By looking at FIG. 2, it will thus be noted that each input terminal (i.e., both the positive input terminal and the negative input terminal) of each ADC should be selectively couplable to both the cathode and the anode of the respective battery cell via dedicated switches, so that each ADC in generic position j can read the voltage of the corresponding battery cell in position j while also allowing to perform a chop function; to this aim, eight switches have to be implemented. In addition, the possibility to implement a swap function is usually demanded for safety, allowing each odd-numbered ADC (e.g., 14i-1) to read the voltage of the corresponding even-numbered cell in the same pair (e.g., Celli) and allowing each even-numbered ADC (e.g., 14i) to read the voltage of the corresponding odd-numbered cell in the same pair (e.g., Celli-1): this implies that each input terminal (i.e., both the positive input terminal and the negative input terminal) of each odd-numbered ADC should also be selectively couplable via dedicated switches to the cathode of the corresponding even-numbered battery cell in the