US-20260128733-A1 - ULTRA LOW POWER CLOCK BUFFER

Abstract

A low-power clock buffer circuit is disclosed that reduces crowbar current and improves power efficiency across a wide range of supply voltages. The circuit comprises an input stage with current-limited PMOS and NMOS transistors, and an output inverter stage with split-gate drive. The input stage uses current sources to control the rise and fall times of signals driving the output inverter, creating a delay between the activation of the PMOS and NMOS transistors in the output stage. This delay minimizes the duration when both output transistors are simultaneously conducting, significantly reducing crowbar current. An alternative embodiment includes a current-starved latch in the output stage to mitigate floating node situations and enhance signal integrity. The circuit is suitable for clock distribution networks in large digital systems.

Inventors

• Sahil Kumar JHA
• Prashutosh GUPTA
• Nitin Jain
• Akshat KUMAR

Assignees

• STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date

20260507

Application Date

20251104

Claims (20)

1. 1 . A low-power clock buffer circuit, comprising: an input stage including: a first PMOS transistor and a first NMOS transistor, each having a gate connected to receive an input signal; a first current source connected to a drain of the first PMOS transistor; and a second current source connected to a drain of the first NMOS transistor; and an output stage including: a second PMOS transistor having a gate connected to the drain of the first PMOS transistor; and a second NMOS transistor having a gate connected to the drain of the first NMOS transistor, wherein currents output by the first and second current sources control timing of signals applied to the gates of the second PMOS and second NMOS transistors to reduce crowbar current in the output stage.
2. 2 . The circuit of claim 1 , further comprising an output buffer connected to drains of the second PMOS transistor and second NMOS transistor.
3. 3 . The circuit of claim 2 , further comprising a current-starved inverter connected in a feedback configuration with the output buffer to form a latch.
4. 4 . The circuit of claim 1 , wherein the first current source is connected between the drain of the first PMOS transistor and ground, and wherein the second current source is connected between a supply voltage and the drain of the first NMOS transistor.
5. 5 . The circuit of claim 1 , wherein the currents output by the first and second current sources control rise and fall times of signals at the drains of the first PMOS and first NMOS transistors, respectively.
6. 6 . The circuit of claim 1 , wherein the input stage and output stage collectively form a low-power inverter with reduced crowbar current.
7. 7 . The circuit of claim 1 , wherein the circuit is configured to operate efficiently across a range of supply voltages in a clock distribution network of a digital system.
8. 8 . A low-power clock buffer circuit, comprising: a first push-pull stage including: a first PMOS transistor and a first NMOS transistor, each having a gate connected to receive a respective input signal, wherein drains of the first PMOS transistor and the first NMOS transistor are connected to form a first output node; a second push-pull stage including: a second PMOS transistor and a second NMOS transistor, each having a gate connected to receive the respective input signal, wherein drains of the second PMOS transistor and the second NMOS transistor are connected to form a second output node; and an output stage including: a third PMOS transistor having a gate connected to the second output node; and a third NMOS transistor having a gate connected to the first output node, wherein the first NMOS transistor and the second PMOS transistor are configured to be stronger than the first PMOS transistor and the second NMOS transistor, respectively, to control timing of signals at the first and second output nodes applied to the gates of the third PMOS and third NMOS transistors to reduce crowbar current in the output stage.
9. 9 . The circuit of claim 8 , further comprising an output buffer connected to drains of the third PMOS transistor and third NMOS transistor.
10. 10 . The circuit of claim 9 , further comprising a current-starved inverter connected in a feedback configuration with the output buffer to form a latch.
11. 11 . The circuit of claim 8 , wherein the first and second push-pull stages control rise and fall times of signals at the first and second output nodes, respectively.
12. 12 . The circuit of claim 8 , wherein the signals at the first and second output nodes cause non-overlapping transitions in the third PMOS transistor and the third NMOS transistor.
13. 13 . A method of operating a clock buffer circuit, the method comprising: receiving an input signal at an input stage; controlling a first current source to limit current flow through a first branch of the input stage; controlling a second current source to limit current flow through a second branch of the input stage; generating a first control signal at a first node between a first transistor and the first current source; generating a second control signal at a second node between a second transistor and the second current source; controlling a turn-on time of a third transistor in an output stage using the first control signal; controlling a turn-on time of a fourth transistor in the output stage using the second control signal; and generating an output signal at an output node formed by a connection between the third and fourth transistors.
14. 14 . The method of claim 13 , further comprising: buffering the output signal using an output buffer; and latching the buffered output signal using a current starved inverter connected between an output of the output buffer and the output node.
15. 15 . The method of claim 13 , wherein controlling the turn-on times of the third and fourth transistors comprises causing one of the third or fourth transistors to turn off before the other turns on, thereby reducing crowbar current in the output stage.
16. 16 . The method of claim 13 , further comprising: transitioning the input signal from a low state to a high state; in response to the low-to-high transition: quickly pulling the second control signal low to turn off the fourth transistor; and slowly discharging the first node to delay turning on the third transistor.
17. 17 . The method of claim 13 , further comprising: transitioning the input signal from a high state to a low state; in response to the high-to-low transition: quickly pulling the first control signal high to turn off the third transistor; and slowly charging the second node to delay turning on the fourth transistor.
18. 18 . The method of claim 13 , wherein the current starved inverter mitigates a floating node condition at the output node when both the third and fourth transistors are off.
19. 19 . The method of claim 13 , wherein the current starved inverter limits the amount of current that can flow through a latch formed by the output buffer and the current starved inverter.
20. 20 . The method of claim 13 , further comprising sharpening edges of the output signal using the combination of the output buffer and the current starved inverter.

Description

RELATED APPLICATION This application claims priority to U.S. Application for Patent No. 63/716,820, filed Nov. 6, 2024, the content of which is incorporated by reference in its entirety. TECHNICAL FIELD This disclosure relates to low-power clock buffer circuits for use in integrated circuits and System-on-Chip (SoC) designs. BACKGROUND Clock buffers are used in modern integrated circuits, particularly in System-on-Chip (SoC) designs, where they are used to improve clock signal integrity as the clock signal traverses the chip. However, these clock buffers face a challenge in the form of high crowbar currents, especially when the input clock signals have poor rise and fall times. This issue directly impacts the power consumption of these buffers, which is a concern in power-sensitive applications. The problem arises from the nature of CMOS inverters which form the basis of many clock buffer designs. In a CMOS inverter, an example of which is illustrated in FIG. 1A, there exists a brief time interval during input transitions when both the PMOS transistor MP1 and NMOS transistor MN1 are simultaneously conducting. This creates a direct path from the supply voltage VDD node to ground, resulting in what is known as crowbar current or short-circuit current, as indicated by the arrow in FIG. 1A. The duration of this crowbar current becomes particularly problematic when the input signal has slow rise and fall times. As shown in the timing diagram in FIG. 1B, a slow transition at the input IN1 of the CMOS inverter prolongs the period during which both transistors MP1 and MN1 are on, leading to increased power consumption. This issue is exacerbated as the supply voltage VDD increases, making it a significant concern for circuits that need to operate across a wide voltage range. Previous attempts to address this issue have included techniques such as the split-inverter approach, illustrated in FIG. 2. This method uses separate inputs INP and INN for the PMOS transistor M1 and NMOS transistor M2 forming the CMOS inverter of interest. Additional transistors M3, M4 & M5 are used to generate INP & INN. Transistor M3 is used to create a DC shift between INP and INN. While this can be effective in reducing short-circuit current, it introduces complexity and may struggle to maintain performance across a wide voltage range. Another attempt, shown in FIG. 3, utilizes a current starving technique. This technique uses DC current sources I1 and I2 to limit the maximum short-circuit current flowing through the inverter formed by transistors M1 and M2. The input stage, formed by transistors M3 and M5, drives the main inverter. A load capacitance CLOAD is shown at the output OUT1. However, this approach can degrade the rise and fall times at the IN2 node if the current limits I1 and I2 are set too low, potentially shifting the problem to subsequent stages in the circuit. Here also, the optimized solution at a particular supply voltage fails to work efficiently across the wide supply voltage range. These limitations in existing designs highlight the need for a more effective approach to designing ultra-low power clock buffers. As such, further development is needed. SUMMARY According to one or more embodiments as described herein, such a result can be achieved via the features set forth in the claims that follow. Embodiments as described herein can also relate to a corresponding system/method. The claims are an integral part of the technical teaching provided herein in respect of the embodiments. A low-power clock buffer circuit includes an input stage and an output stage. The input stage has a first PMOS transistor and a first NMOS transistor, each having a gate connected to receive an input signal. A first current source is connected to a drain of the first PMOS transistor. A second current source is connected to a drain of the first NMOS transistor. The output stage has a second PMOS transistor having a gate connected to the drain of the first PMOS transistor. A second NMOS transistor has a gate connected to the drain of the first NMOS transistor. The first and second current sources control timing of signals applied to the gates of the second PMOS and second NMOS transistors to reduce crowbar current in the output stage. The circuit may have an output buffer connected to drains of the second PMOS and second NMOS transistors. The circuit may have a current-starved inverter connected in a feedback configuration with the output buffer to form a latch. The first current source may be connected between the drain of the first PMOS transistor and ground, and the second current source may be connected between a supply voltage and the drain of the first NMOS transistor. The first and second current sources may control rise and fall times of signals at the drains of the first PMOS and first NMOS transistors, respectively. The input stage and output stage may collectively form a low-power inverter with reduced crowbar current. The circuit may