US-20260128734-A1 - PULSE OUTPUT DEVICE, LASER SYSTEM AND METHOD FOR OUTPUTTING PULSES

US20260128734A1US 20260128734 A1US20260128734 A1US 20260128734A1US-20260128734-A1

Abstract

A pulse output device includes a digital pulse generator for outputting at least one output pulse triggered by a trigger signal. The digital pulse generator has a trigger input for the trigger signal and a clock input for a clock signal. The pulse output device further includes a clock generator for generating the clock signal, and a clock splitter. For synchronization of the clock signal with the trigger signal, the pulse output device is configured to stop the clock splitter, which is configured to reduce a clock rate of the clock signal, and/or to stop the clock generator before the clock signal is fed to the clock input of the digital pulse generator, and to restart the clock splitter and/or the clock generator synchronously with the trigger signal.

Inventors

Michael Harteker
Rainer Flaig
Oliver Rapp
Thomas Haas

Assignees

TRUMPF Laser SE

Dates

Publication Date: 20260507
Application Date: 20260105
Priority Date: 20230711

Claims (10)

1 . A pulse output device, comprising: a digital pulse generator for outputting at least one output pulse triggered by a trigger signal, wherein the digital pulse generator has a trigger input for the trigger signal and a clock input for a clock signal, a clock generator for generating the clock signal, and a clock splitter, wherein, for synchronization of the clock signal with the trigger signal, the pulse output device is configured to stop the clock splitter, which is configured to reduce a clock rate of the clock signal, and/or to stop the clock generator before the clock signal is fed to the clock input of the digital pulse generator, and to restart the clock splitter and/or the clock generator synchronously with the trigger signal.
2 . The pulse output device according to claim 1 , further comprising a feed device for feeding the trigger signal to the clock splitter and/or to the clock generator.
3 . The pulse output device according to claim 2 , wherein the clock splitter and/or the clock generator is/are configured to stop on a first edge of the trigger signal and to restart on a second edge of the trigger signal.
4 . The pulse output device according to claim 1 , further comprising a delay device for delaying the trigger signal before the trigger signal is fed to the trigger input of the digital pulse generator.
5 . The pulse output device according to claim 1 , further comprising a clock distributor for distributing the clock signal synchronized with the trigger signal.
6 . The pulse output device according to claim 1 , wherein the digital pulse generator is configured to delay the output pulse by a predetermined number of clock cycles of the clock signal.
7 . The pulse output device according to claim 1 , wherein the clock splitter is used to reduce the clock rate of the clock signal generated by the clock generator by at least 1:8.
8 . The pulse output device according to claim 1 , wherein the digital pulse generator is configured as a field-programmable gate arrays (FPGA) or as a microcontroller.
9 . A laser system comprising: a pulse output device according to claim 1 , and a laser source for generating at least one laser pulse, wherein the laser pulse is synchronized with the at least one output pulse output by the digital pulse generator.
10 . A method for outputting, by a digital pulse generator, at least one output pulse triggered by a trigger signal, the method comprising: feeding the trigger signal to a trigger input of the digital pulse generator, feeding a clock signal to a clock input of the digital pulse generator, outputting, by the digital pulse generator, the at least one output pulse triggered by the trigger signal, and for synchronization of the clock signal with the trigger signal, stopping a clock generator for generating the clock signal and/or a clock splitter for reducing a clock rate of the clock signal before the clock signal is fed to the clock input of the digital pulse generator, and restarting the clock generator and/or the clock splitter synchronously with the trigger signal.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation of International Application No. PCT/EP2024/069631 (WO 2025/012370 A1), filed on Jul. 11, 2024, and claims benefit to German Patent Application No. DE 10 2023 118 275.7, filed on Jul. 11, 2023. The aforementioned applications are hereby incorporated by reference herein. FIELD Embodiments of the present invention relate to a pulse output device. Embodiments of the present invention also relate to a laser system which has such a pulse output device, and to a method for outputting by a digital pulse generator at least one pulse triggered by a trigger signal. BACKGROUND The digital pulse generator is used for discrete sampling or discrete reading of the (external) trigger signal. When the external event (trigger), which is non-synchronous with the clock, is read by the digital pulse generator, a temporal discretization of the event occurs, as in all digital clock-based systems, which leads to a jitter (clock jitter) relative to the external trigger signal. The jitter is primarily determined by the chosen base clock of the clock signal or the sampling rate of the discrete or digital clock-based system. For many applications, the occurrence of jitter is undesirable, as synchronization with other systems or components is no longer possible in an ideal manner. The digital pulse generator or pulse output device can, for example, be used to control a laser source of an (ultrashort pulse) laser system in order to use the laser system in “pulse-on-demand” operation, i.e., to generate laser pulses with freely selectable triggering. A digital pulse generator of a laser control system of such a laser system typically operates with clock signals which have clock rates in the order of approximately 50 MHz to approximately 100 MHz or possibly up to 200 MHz. When clock rates of the order of magnitude described here are used to sample an external, random trigger signal (e.g., for a laser pulse request), a discrete jitter in the order of +/−5 ns is typically generated. A reduction in jitter could be achieved by increasing the sampling rate or clock rate of the digital pulse generator, but this would result in an increase in the costs of the electronic components. Furthermore, increasing the clock rate of the digital pulse generator is technically limited. To synchronize circuit components, phase-locked loops are typically used, which typically do not require a trigger event, but rather a recurring clock signal to which another clock signal can synchronize. Furthermore, this process requires several clock edges of the external signal, which necessitates a duration in the order of approximately 10 to 100 μs. CN112968690A describes a high-precision pulse generator with low jitter. The pulse generator features a time-to-digital converter module in the form of an FPGA, which determines the time interval between the external trigger signal and the clock signal in order to compensate for the jitter output of the pulse. A jitter compensation module processes the time information measured by the time-to-digital converter module and the delay time specified by an operator to obtain the final delay information for pulse compensation. The delay should achieve a precision of 22 ps, and the jitter of the output pulse should be 500 ps. TW201249107A describes a mechanism for generating an event-triggered pulse wave, which comprises a microcontroller. The width of the output pulse wave can be adjusted to the clock width of a clock signal using an algorithm, and the rising edge of the system can be synchronized. The microcontroller has two interrupt terminals for this purpose. SUMMARY Embodiments of the present invention provide a pulse output device. The pulse output device includes a digital pulse generator for outputting at least one output pulse triggered by a trigger signal. The digital pulse generator has a trigger input for the trigger signal and a clock input for a clock signal. The pulse output device further includes a clock generator for generating the clock signal, and a clock splitter. For synchronization of the clock signal with the trigger signal, the pulse output device is configured to stop the clock splitter, which is configured to reduce a clock rate of the clock signal, and/or to stop the clock generator before the clock signal is fed to the clock input of the digital pulse generator, and to restart the clock splitter and/or the clock generator synchronously with the trigger signal. BRIEF DESCRIPTION OF THE DRAWINGS Subject matter of the present disclosure will be described in even greater detail below based on the exemplary figures. All features described and/or illustrated herein can be used alone or combined in different combinations. The features and advantages of various embodiments will become apparent by reading the following detailed description with reference to the attached drawings, which illustrate the following: FIG. 1 shows a schematic re