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US-20260128735-A1 - DELAY CIRCUIT AND OPERATIONAL METHOD THEREOF

US20260128735A1US 20260128735 A1US20260128735 A1US 20260128735A1US-20260128735-A1

Abstract

A circuit is provided. The circuit comprises a first power switch, a second power switch and delay elements. The first power switch adjusts a first voltage on a first metal line according to an input signal. The second power switch adjusts a second voltage on a second metal line according to the first voltage. The delay elements are coupled between the first metal line and the second metal line, and delay, in response to the adjusted first voltage and the adjusted second voltage, the input signal to generate an output signal.

Inventors

  • Masaya Hamada
  • Makoto Yabuuchi

Assignees

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Dates

Publication Date
20260507
Application Date
20251229

Claims (20)

  1. 1 . A circuit, comprising: a first power switch configured to provide a first voltage to a first metal line in response to an input signal; a second power switch configured to provide a second voltage to a second metal line according in response to the first voltage; and a plurality of delay elements coupled in series and powered by the first voltage on the first metal line and the second voltage on the second metal line, wherein the delay elements are configured to generate, in response to the second voltage, an output signal that is a delayed version of the input signal.
  2. 2 . The circuit of claim 1 , wherein the plurality of delay elements are logic gates coupled in series.
  3. 3 . The circuit of claim 1 , wherein the first voltage and the second voltage are supply voltages of the plurality of delay elements, wherein the first voltage is smaller than the second voltage.
  4. 4 . The circuit of claim 1 , wherein the first power switch is a first inverter, wherein an input terminal of the first inverter is coupled to the input signal and an output terminal of the first inverter is coupled to the first metal line, wherein the second power switch is a second inverter, wherein an input terminal of the second inverter is coupled to the first metal line and an output terminal of the first inverter is coupled to the second metal line.
  5. 5 . The circuit of claim 4 , wherein an input terminal of a first delay element of the plurality of delay elements is coupled to the second metal line.
  6. 6 . The circuit of claim 1 , wherein the plurality of delay elements comprise a plurality of NAND gates and a plurality of NOR gates that are coupled in series alternatively.
  7. 7 . The circuit of claim 6 , wherein the plurality of NOR gates are configured to receive a third voltage as a VSS source and are coupled to the second metal line to receive the second voltage as a VDD source.
  8. 8 . The circuit of claim 7 , wherein the plurality of NAND gates are configured to receive a fourth voltage as a VDD source and are coupled to the first metal line to receive the first voltage as a VSS source, wherein the fourth voltage is higher than the third voltage.
  9. 9 . The circuit of claim 6 , further comprising: a first NAND gate, wherein a first input terminal of the first NAND gate is coupled to the second metal line and a second input terminal of the first NAND gate is coupled to the input signal, wherein a first input terminal of a first NOR gate of the plurality of NOR gates is coupled to an output terminal of the first NAND gate and a second input terminal of the first NOR gate is coupled to the first metal line.
  10. 10 . The circuit of claim 9 , wherein a first input terminal of a second NAND gate of the plurality of NAND gates is coupled to the second metal line and a second input terminal of the second NAND gate is coupled to an output terminal of the first NOR gate.
  11. 11 . The circuit of claim 6 , further comprising: a first NOR gate powered by the first voltage and a ground voltage, wherein a first input terminal of the first NOR gate is coupled to the second metal line, a second input terminal of the first NOR gate is coupled to the input signal and an output terminal of the first NOR gate is coupled to the plurality of delay elements to delay the input signal.
  12. 12 . A circuit comprising: a first power switch coupled to a first metal line and configured to provide a first voltage on the first metal line in response to an input signal; a second power switch that is coupled between the first metal line and a second metal line and is configured to provide a second voltage on the second metal line in response to the first voltage; a first delay element powered by the first voltage and a third voltage, wherein the first delay element is configured to delay the input signal for generating a delayed signal of the input signal; and a second delay element powered by the second voltage and a fourth voltage, wherein the second delay element is configured to generate a further delayed signal in response to the delayed signal.
  13. 13 . The circuit of claim 12 , wherein the first delay element is a NAND gate comprising an input terminal coupled to the second metal line, wherein the second delay element is a NOR gate comprising an input terminal coupled to the first metal line.
  14. 14 . The circuit of claim 13 , further comprising: a third delay element that is a NAND gate, wherein a first input terminal of the third delay element is coupled to the second metal line and a second input terminal of the third delay element is coupled to an output terminal of the second delay element; and a fourth delay element that is a NOR gate, wherein a first input terminal of the fourth delay element is coupled to the output terminal of the third delay element and a second input terminal of the fourth delay element is coupled to the first metal line.
  15. 15 . The circuit of claim 14 , wherein the first metal line is in a first semiconductor layer, wherein the first power switch comprises a first conductive segment in a second semiconductor layer under the first semiconductor layer and the first power switch is coupled to the first metal line through the first conductive segment, wherein the first delay element comprises a second conductive segment in the second semiconductor layer and the first delay element is coupled to the first metal line through the second conductive segment, wherein the third delay element comprises the second conductive segment and is coupled to the first metal line through the second conductive segment.
  16. 16 . The circuit of claim 15 , wherein the first conductive segment and the second conductive segment are coupled to a first active region, wherein the first active region and the first metal line extend along a first direction.
  17. 17 . The circuit of claim 16 , wherein the first conductive segment corresponds to an output terminal of the first power switch, and the second conductive segment corresponds to power terminals of the first and third delay element.
  18. 18 . The circuit of claim 16 , wherein the second metal line is in the first semiconductor layer, wherein the second power switch comprises a third conductive segment in the second semiconductor and the second power switch is coupled to the second metal line through the third conductive segment, wherein the second delay element comprises a fourth conductive segment in the second semiconductor layer and the second delay element is coupled to the second metal line through the fourth conductive segment, wherein the fourth delay element comprises the fourth conductive segment and is coupled to the second metal line through the fourth conductive segment, wherein the third conductive segment and the fourth conductive segment are coupled to a second active region separated from the first active region along a second direction different from the first direction.
  19. 19 . A method, comprising: providing, by a first power switch, a first voltage to a first metal line in response to an input signal; providing, by a second power switch, a second voltage to a second metal line in response to the first voltage; powering up a plurality of delay elements by the first and second voltages; and generating an output signal that is a delayed version of the input signal in response to the second voltage.
  20. 20 . The method of claim 19 , further comprising: transmitting the input signal to the plurality of delay elements; and pulling down the output signal through the plurality of delay elements in response to the input signal pulled down after a delay time.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a continuation application of U.S. application Ser. No. 18/770,907, filed Jul. 12, 2024, which is incorporated by reference herein in its entirety. BACKGROUND A delay circuit is usually implemented with a lot of logic gates or long metal lines to make a delay time. To generate a long delay time, the delay circuit needs to use many transistors for the logic gates or a lot of metal to form a long enough metal line. In such manner, a lot of resource and area is used. With the increasing integration and shrinking scale of electronic devices, it is important to provide a delay circuit with better resource and area efficiency. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a schematic diagram of a delay circuit, in accordance with some embodiments of the present disclosure. FIG. 2 is a timing diagram of voltage levels of signals corresponding to the delay circuit of FIG. 1, in accordance with some embodiments of the present disclosure. FIG. 3 is a schematic diagram of a delay circuit configured with respect to the delay circuit of FIGS. 1-2, in accordance with some embodiments of the present disclosure. FIG. 4A is a schematic diagram corresponding to the power switches of the delay circuit of FIG. 3, in accordance with some embodiments of the present disclosure. FIG. 4B is a schematic diagram corresponding to the delay elements of the delay circuit of FIG. 3, in accordance with some embodiments of the present disclosure. FIG. 4C is a schematic diagram corresponding to the delay elements of the delay circuit of FIG. 3, in accordance with some embodiments of the present disclosure. FIG. 5 is a timing diagram of voltage levels of signals corresponding to the delay circuit 20 of FIGS. 3 and 4A-4C, in accordance with some embodiments of the present disclosure. FIG. 6A is a schematic diagram of a delay circuit configured with respect to the delay circuit of FIGS. 1-3, 4A-4C, 5, in accordance with some embodiments of the present disclosure. FIG. 6B is a layout diagram of the delay circuit of FIG. 6A in a top view, in accordance with some embodiments of the present disclosure. FIG. 7 is a schematic diagram of a delay circuit configured with respect to the delay circuit of FIGS. 1-3, 4A-4C, 5, 6A-6B, in accordance with some embodiments of the present disclosure. FIG. 8 is a timing diagram of voltage levels of signals corresponding to the delay circuit of FIG. 8, in accordance with some embodiments of the present disclosure. FIG. 9A is a schematic diagram of a delay circuit configured with respect to the delay circuit of FIGS. 1-2, 7-8, in accordance with some embodiments of the present disclosure. FIG. 9B is a layout diagram of the delay circuit of FIG. 6A in a top view, in accordance with some embodiments of the present disclosure. FIG. 10 is a flow chart diagram of a method for operating the delay circuit, in accordance with some embodiments of the present disclosure. FIG. 11 is a block diagram of an electronic design automation (EDA) system for designing the integrated circuit layout design, in accordance with some embodiments of the present disclosure. FIG. 12 is a block diagram of IC manufacturing system, and an IC manufacturing flow associated therewith, in accordance with some embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements or the like are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements or the like are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to an