US-20260128736-A1 - CLOCK GLITCH DETECTION CIRCUIT AND METHOD THEREOF

US20260128736A1US 20260128736 A1US20260128736 A1US 20260128736A1US-20260128736-A1

Abstract

The present application discloses a clock glitch detection circuit including a clock generator, a counter, and a detection unit. The clock generator receives an input clock signal, and generates a reference clock signal having a frequency higher than that of the input clock signal when the input clock signal is at a first voltage. The counter counts a current accumulated number of cycles of the reference clock signal that occur while the input clock signal is at the first voltage. The detection unit calculates a difference between the previous and the current accumulated numbers after the input clock signal changes from the first voltage to a second voltage. The detection unit generates an alarm signal according to the difference between the previous and the current accumulated numbers and stores the current accumulated number as the previous accumulated number.

Inventors

Chi-Yi Shao
Sheng-Tsung Wang
CHIH-NI WU

Assignees

PUFsecurity Corporation

Dates

Publication Date: 20260507
Application Date: 20251030

Claims (20)

1 . A clock glitch detection circuit comprising: a first clock generator configured to receive an input clock signal, and generate a first reference clock signal when the input clock signal is at a first voltage, wherein a frequency of the first reference clock signal is higher than a frequency of the input clock signal; a first counter configured to count a first current accumulated number of cycles of the first reference clock signal that occur while the input clock signal is at the first voltage in a counting phase; and a first detection unit configured to calculate a difference between a first previous accumulated number and the first current accumulated number after the input clock signal changes from the first voltage to a second voltage in a judging phase later than the counting phase, and, after the difference between the first previous accumulated number and the first current accumulated number is calculated, store the first current accumulated number as the first previous accumulated number and generate a first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number.
2 . The clock glitch detection circuit of claim 1 , further comprising: a first sequential control unit configured to generate a first sequential control signal when the input clock signal changes from the first voltage to the second voltage, and generate a first control signal in the judging phase by delaying the first sequential control signal; wherein the first detection unit is triggered to calculate the difference between the first previous accumulated number and the first current accumulated number according to the first control signal.
3 . The clock glitch detection circuit of claim 2 , wherein the first sequential control unit is further configured to generate a second control signal in the judging phase by delaying the first control signal; wherein the first detection unit is triggered to generate the first alarm signal and store the first current accumulated number as the first previous accumulated number according to the second control signal.
4 . The clock glitch detection circuit of claim 3 , wherein the first sequential control unit is further configured to generate a third control signal in the judging phase by delaying the second control signal; wherein the first counter is reset when receiving the third control signal.
5 . The clock glitch detection circuit of claim 4 , wherein the first sequential control unit comprises: an SR latch comprising a set terminal configured to receive an inversed input clock signal, a reset terminal configured to receive the third control signal, and a data output terminal configured to output the first sequential control signal after the input clock signal changes to the second voltage; and a delay control unit configured to generate the first control signal, the second control signal, and the third control signal according to the first sequential control signal.
6 . The clock glitch detection circuit of claim 3 , wherein the first detection unit comprises: a register configured to store the first currently accumulated number as the first previous accumulated number when receiving the second control signal; and a subtractor configured to subtract the first previous accumulated number from the first current accumulated number or subtract the first current accumulated number from the first previous accumulated number so as to calculate the difference between the first previous accumulated number and the first current accumulated number when receiving the first control signal.
7 . The clock glitch detection circuit of claim 6 , wherein a first delay between the first sequential control signal and the first control signal is longer than a calculating time of the subtractor.
8 . The clock glitch detection circuit of claim 6 , wherein the subtractor comprises: a carry look ahead subtractor configured to continuously perform a subtract operation upon the first current accumulated number and the first previous accumulated number to calculate the difference between the first previous accumulated number and the first current accumulated number; and a register configured to be triggered by the first control signal to store the difference between the first previous accumulated number and the first current accumulated number.
9 . The clock glitch detection circuit of claim 6 , wherein the first detection unit further comprises: a compare logic circuit configured to generate the first alarm signal in the judging phase when receiving the second control signal and when the difference between the first previous accumulated number and the first current accumulated number is greater than a predetermined value.
10 . The clock glitch detection circuit of claim 9 , wherein the compare logic circuit comprises: a logic circuit configured to continuously obtain a comparison result between the difference calculated by the subtractor and the predetermined value; and a register configured to be triggered by the second control signal to store the comparison result between the difference calculated by the subtractor and the predetermined value.
11 . The clock glitch detection circuit of claim 9 , a second delay between the first control signal and the second control signal is longer than a calculating time of the compare logic circuit.
12 . The clock glitch detection circuit of claim 1 , wherein the first detection unit generates the first alarm signal in the judging phase when the difference between the first previous accumulated number and the first current accumulated number is greater than a predetermined value.
13 . The clock glitch detection circuit of claim 1 , wherein the first clock generator is disabled when the input clock signal is at the second voltage.
14 . The clock glitch detection circuit of claim 1 , further comprising: a third inverter configured to generate an inversed input clock signal by inversing the input clock signal; a second clock generator configured to receive the inversed input clock signal, and generate a second reference clock signal when the inversed input clock signal is at the first voltage, wherein a frequency of the second reference clock signal is higher than a frequency of the inversed input clock signal; a second counter configured to count a second current accumulated number of cycles of the second reference clock signal; and a second detection unit configured to calculate a difference between a second previous accumulated number and the second current accumulated number after the inversed input clock signal changes from the first voltage to the second voltage, and, after the difference between the second previous accumulated number and the second current accumulated number is calculated, generate a second alarm signal according to the difference between the second previous accumulated number and the second current accumulated number and store the second current accumulated number as the second previous accumulated number.
15 . The clock glitch detection circuit of claim 14 , further comprising: a second sequential control unit configured to generate a second sequential control signal when the inversed input clock signal changes from the first voltage to the second voltage, and generate a fourth control signal by delaying the second sequential control signal; wherein the second detection unit is triggered to calculate the difference between the second previous accumulated number and the second current accumulated number according to the fourth control signal.
16 . The clock glitch detection circuit of claim 15 , wherein the second sequential control unit is further configured to generate a fifth control signal by delaying the fourth control signal and a sixth control signal by delaying the fifth control signal; wherein the second detection unit is triggered to generate the second alarm signal and store the second current accumulated number as the second previous accumulated number according to the fifth control signal, and the second counter is reset when receiving the sixth control signal.
17 . A method for detecting clock glitches of an input clock signal with a clock glitch detection circuit, wherein the clock glitch detection circuit comprises a first clock generator, a first counter, and a first detection unit, and the method comprises: generating, by the first clock generator, a first reference clock signal when the input clock signal is at a first voltage, wherein a frequency of the first reference clock signal is higher than a frequency of the input clock signal; counting, by the first counter, a first current accumulated number of cycles of the first reference clock signal; calculating, by the first detection unit, a difference between a first previous accumulated number and the first current accumulated number after the input clock signal changes from the first voltage to a second voltage; generating, by the first detection unit, a first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number after the difference between a first previous accumulated number and the first current accumulated number is calculated; and storing, by the first detection unit, the first current accumulated number as the first previous accumulated number after the difference is calculated.
18 . The method of claim 17 , wherein the clock glitch detection circuit further comprises a first sequential control unit, and the method further comprises: generating, by the first sequential control unit, a first sequential control signal when the input clock signal changes from the first voltage to the second voltage; and generating, by the first sequential control unit, a first control signal by delaying the first sequential control signal; wherein the difference between the first previous accumulated number and the first current accumulated number is calculated when the first detection unit receives the first control signal.
19 . The method of claim 18 , further comprising: generating, by the first sequential control unit, a second control signal by delaying the first control signal; wherein the step of generating, by the first detection unit, the first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number and the step of storing, by the first detection unit, the first current accumulated number as the first previous accumulated number are performed when the first detection unit receives the second control signal.
20 . The method of claim 19 , further comprising: generating, by the sequential control unit, a third control signal by delaying the second control signal; and resetting the first counter when receiving the third control signal.

Description

TECHNICAL FIELD The present disclosure relates to a glitch detection circuit, and more particularly, to a glitch detection circuit capable of detecting glitch in a clock signal. DISCUSSION OF THE BACKGROUND The clock signal is a critical component in electronic circuits, serving as the timing reference that synchronizes operations across various elements within the system. The precise periodicity of the clock signal ensures that data is processed in a coordinated manner, thereby facilitating the seamless execution of complex computational tasks. Consequently, even minor deviations or distortions in the clock signal (i.e., glitches) can adversely affect the circuit performance. For example, the glitch can lead to erroneous data sampling, signal interference, and misalignment of the system's state, potentially causing malfunction or failure of the entire circuit. Therefore, it is crucial to detect the clock signal glitch and avoid the malfunction or failure of the system. SUMMARY One aspect of the present disclosure provides a clock glitch detection circuit. The clock glitch detection circuit includes a clock generator, a counter, a detection unit, and a sequential control unit. The clock generator receives an input clock signal, and generates a first reference clock signal when the input clock signal is at a first voltage. A frequency of the reference clock signal is higher than a frequency of the input clock signal. The counter counts a current accumulated number of cycles of the reference clock signal that occur while the input clock signal is at the first voltage. The detection unit calculates a difference between a previous accumulated number and the current accumulated number after the input clock signal changes from the first voltage to a second voltage, and, after the difference between the previous accumulated number and the current accumulated number is updated, generate an alarm signal according to the difference between the previous accumulated number and the current accumulated number and store the current accumulated number as the previous accumulated number. Another aspect of the present disclosure provides a method for detecting clock glitches of an input clock signal with a clock glitch detection circuit. The clock glitch detection circuit includes a clock generator, a counter, and a detection unit. The method includes generating, by the clock generator, a first reference clock when the input clock signal is at a first voltage, counting, by the counter, a first current accumulated number of cycles of the first reference clock signal that occur while the input clock signal is at the first voltage, calculating, by the detection unit, a difference between a first previous accumulated number and the first current accumulated number after the input clock signal changes from the first voltage to a second voltage, generating, by the detection unit, a first alarm signal according to the difference between the first previous accumulated number and the first current accumulated number after the difference between a first previous accumulated number and the first current accumulated number is updated, and storing, by the detection unit, the first current accumulated number as the first previous accumulated number. A frequency of the first reference clock signal is higher than a frequency of the input clock signal. BRIEF DESCRIPTION OF THE PLOTTINGS A more complete understanding of the present disclosure may be derived by referring to the detailed description and claims when considered in connection with the Figures, where like reference numbers refer to similar elements throughout the Figures. FIG. 1 shows a clock glitch detection circuit according to one embodiment of the present disclosure. FIG. 2 shows a signal timing diagram of the clock glitch detection circuit in FIG. 1 according to one embodiment of the present disclosure. FIG. 3 shows the logic circuit according to one embodiment of the present disclosure. FIG. 4 shows a clock glitch detection circuit according to one embodiment of the present disclosure. FIG. 5 shows a method for detecting clock glitches of the input clock signal according to one embodiment of the present disclosure. DETAILED DESCRIPTION FIG. 1 shows a clock glitch detection circuit 100 according to one embodiment of the present disclosure. The clock glitch detection circuit 100 includes a clock generator 110, a counter 120, and a detection unit 130. In the present embodiment, the clock glitch detection circuit 100 is designed to detect glitches in an input clock signal SIGCKIN that toggles between voltages V1 and V2. The clock generator 110 can receive the input clock signal SIGCKIN, generate a reference clock signal SIGREF1 when the input clock signal SIGCKIN is at the voltage VI, and stop generating the reference clock signal SIGREF1 when the input clock signal SIGCKIN is at the voltage V2. That is, the clock generator 110 can be enabled when the input clock signal SIGCKIN i