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US-20260128737-A1 - ELECTROSTATIC DISCHARGE LOCK CIRCUIT FOR OUTPUT DRIVER

US20260128737A1US 20260128737 A1US20260128737 A1US 20260128737A1US-20260128737-A1

Abstract

The present invention provides a circuitry including an output driver and an ESD lock circuit. The output driver includes a first transistor and a second transistor, wherein the first transistor is coupled between an I/O pad and a ground voltage, and the second transistor is coupled between the I/O pad and a supply voltage. The ESD lock circuit is coupled between the I/O pad and the ground voltage, and is configured to generate a control signal to control the first transistor according to a voltage at the I/O pad.

Inventors

  • Shih-Chun Yen
  • Shao Siang NG

Assignees

  • MEDIATEK INC.

Dates

Publication Date
20260507
Application Date
20250721

Claims (10)

  1. 1 . A circuitry, comprising: an output driver comprises a first transistor and a second transistor, wherein the first transistor is coupled between an input/output (I/O) pad and a ground voltage, and the second transistor is coupled between the I/O pad and a supply voltage; and an electrostatic discharge (ESD) lock circuit, coupled between the I/O pad and the ground voltage, configured to generate a control signal to control the first transistor according to a voltage at the I/O pad.
  2. 2 . The circuitry of claim 1 , wherein the circuitry selectively operates in an ESD testing mode or a normal mode; and when the circuitry operates in the ESD testing mode, the ESD lock circuit receives the voltage at the I/O pad to generate the control signal to disable the first transistor.
  3. 3 . The circuitry of claim 2 , further comprises: two pre-drivers; wherein when the circuitry operates in the normal mode, the ESD lock circuit is disabled, and the two pre-drivers are configured to generate two driving signals to control the first transistor and the second transistor, to generate an output signal to the I/O pad.
  4. 4 . The circuitry of claim 1 , wherein the ESD lock circuit comprises: a third transistor, coupled between a gate electrode of the first transistor and the ground voltage; and a fourth transistor, configured to selectively couple the I/O pad to a gate electrode of the third transistor.
  5. 5 . The circuitry of claim 4 , wherein the first transistor, the third transistor and the fourth transistor are N-type transistors, a drain electrode of the third transistor is used to generate the control signal to the gate electrode of the first transistor, a source electrode of the third transistor is coupled to the ground voltage, a drain electrode of the fourth transistor is coupled to the I/O pad, and a gate electrode and a source electrode of the fourth transistor are coupled to the gate electrode of the third transistor.
  6. 6 . The circuitry of claim 5 , wherein the gate electrode of the fourth transistor does not directly connect to the I/O pad, and the gate electrode of the fourth transistor only couples the I/O pad via a parasitic capacitor.
  7. 7 . The circuitry of claim 5 , further comprising: a switch, configured to selectively couple the gate electrode of the fourth transistor to the ground voltage.
  8. 8 . The circuitry of claim 7 , wherein the circuitry selectively operates in an ESD testing mode or a normal mode; and when the circuitry operates in the ESD testing mode, the switch is disabled, and the gate electrode of the fourth transistor receives a coupled signal with high voltage level via a gate-drain parasitic capacitance of the fourth transistor when the I/O pad has the voltage with high voltage level, so that the fourth transistor and the third transistor are enabled to generate the control signal to disable the first transistor.
  9. 9 . The circuitry of claim 8 , wherein when the circuitry operates in the normal mode, the switch is enabled, and the fourth transistor and the third transistor are disabled so that the drain electrode of the third transistor is at a floating state.
  10. 10 . The circuitry of claim 7 , wherein the switch is implemented by the N-type transistor.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Application No. 63/716,243, filed on November 5th, 2024. The content of the application is incorporated herein by reference. BACKGROUND FIG. 1 is a conventional circuitry 100 comprising an output driver 110. As shown in FIG. 1, the circuitry 100 further comprises two pre-drivers 120, 130, an electrostatic discharge (ESD) clamping circuit 140 and an input/output (I/O) pad 102. The output driver 110 comprises an N-type transistor M1 and a P-type transistor M2 connected between a supply voltage VDD and a ground voltage, wherein a connection node coupled between a drain electrode of the P-type transistor M2 and a drain electrode of the N-type transistor M1 is coupled to the I/O pad 102, for receiving an input signal from another device or transmitting an output signal to other devices. The pre-drivers 120 and 130 are configured to enable or disable the N-type transistor M1 and the P-type transistor M2, respectively, to generate the output signal to the other devices via the I/O pad 102. The ESD clamping circuit 140 is configured to provide a current path when the supply voltage VDD is higher than a threshold voltage. Generally, N-type transistor M1 and the P-type transistor M2 in the output driver 110 are designed to have larger sizes to provide better driving capability or self-protection. However, transistors with larger sizes also have larger gate-drain parasitic capacitances, such as Cgd1 of the N-type transistor M1 and Cgd2 of the P-type transistor M2 shown in FIG. 1. Therefore, if the pad 102 suddenly receives a high voltage, this high voltage will be coupled to the gate electrode of the N-type transistor M1 through the parasitic capacitance Cgd1, which may cause the N-type transistor M1 to be damaged due to this high voltage. Moreover, since transistors made using current advanced semiconductor processes typically have lower voltage endurance, the likelihood of the N-type transistor being damaged by this high voltage is further increased. SUMMARY It is therefore an objective of the present invention to provide circuitry, which design an ESD lock circuit to disable the N-type transistor when the I/O pad suffer high voltage, to solve the above-mentioned problems. According to one embodiment of the present invention, a circuitry comprising an output driver and an ESD lock circuit is disclosed. The output driver comprises a first transistor and a second transistor, wherein the first transistor is coupled between an I/O pad and a ground voltage, and the second transistor is coupled between the I/O pad and a supply voltage. The ESD lock circuit is coupled between the I/O pad and the ground voltage, and is configured to generate a control signal to control the first transistor according to a voltage at the I/O pad. These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a conventional circuitry comprising an output driver. FIG. 2 is a diagram illustrating a circuitry according to one embodiment of the present invention. FIG. 3 shows the ESD lock circuit and the operation of the circuitry show in FIG. 2 when operating in an ESD testing mode according to one embodiment of the present invention. FIG. 4 shows the ESD lock circuit and the operation of the circuitry show in FIG. 2 when operating in a normal mode according to one embodiment of the present invention. DETAILED DESCRIPTION Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to …”. The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. FIG. 2 is a diagram illustrating a circuitry 200 according to one embodiment of the present invention. As shown in FIG. 2, the circuitry 200 comprises an output driver 210, two pre-drivers 220, 230, an ESD clamping circuit 240, an ESD lock circuit 250 and an I/O pad 202. The output driver 210 comprises two transistors M1 and M2 that are implemented by N-type transistor (e.g., N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)) and P-type transistor (e.g., P-type MOSFET), respectively, wher