US-20260128741-A1 - RECEIVER CIRCUIT WITH PARALLEL TRIGGER CIRCUITRY

Abstract

Receiver circuits, integrated circuits containing such receiver circuits, and related methods are described. For example, a receiver circuit includes first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit, and second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.

Inventors

• Sneha SHETTY
• Rajesh Yadav

Assignees

• TEXAS INSTRUMENTS INCORPORATED

Dates

Publication Date

20260507

Application Date

20241106

Claims (20)

1. 1 . A receiver circuit, comprising: first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit; and second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level; wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
2. 2 . The receiver circuit of claim 1 , further comprising control circuitry configured to concurrently enable the first and second trigger circuitry responsive to an applied control signal.
3. 3 . The receiver circuit of claim 1 , wherein the first trigger circuitry is configured to drive the output node of the receiver circuit to one of a logic high level and a logic low level responsive to the low-to-high transition of the input signal and the second trigger circuitry is configured to drive the output node of the receiver circuit to the other of the logic high level and the logic low level responsive to the high-to-low transition of the input signal.
4. 4 . The receiver circuit of claim 1 , wherein the first and second trigger circuitry comprise respective first and second inverters, each of the first and second inverters having an input coupled to the input node of the receiver circuit and an output coupled to the output node of the receiver circuit.
5. 5 . The receiver circuit of claim 4 , wherein each of the first and second inverters comprises a first P-type field effect transistor and a first N-type field effect transistor, each having a gate terminal, a source terminal and a drain terminal, the gate terminals being coupled to the input node of the receiver circuit, the source terminal of the first P-type field effect transistor being coupled to an upper supply terminal of the receiver circuit, the drain terminal of the first P-type field effect transistor being coupled to the drain terminal of the first N-type field effect transistor, and the source terminal of the first N-type field effect transistor being coupled to a lower supply terminal of the receiver circuit.
6. 6 . The receiver circuit of claim 5 , wherein the first trigger circuitry further comprises an additional P-type field effect transistor having a gate terminal coupled to the respective drain terminals of the first P-type field effect transistor and the first N-type field effect transistor of the first inverter, a source terminal coupled to the upper supply terminal, and a drain terminal coupled to the output node of the receiver circuit.
7. 7 . The receiver circuit of claim 5 , wherein the second trigger circuitry further comprises an additional N-type field effect transistor having a gate terminal coupled to the respective drain terminals of the first P-type field effect transistor and the first N-type field effect transistor of the second inverter, a source terminal coupled to the lower supply terminal, and a drain terminal coupled to the output node of the receiver circuit.
8. 8 . The receiver circuit of claim 4 , wherein channel sizes of respective P-type and N-type field effect transistors of the first inverter are configured in a first ratio that at least partially sets the first trigger level, and channel sizes of respective P-type and N-type field effect transistors of the second inverter are configured in a second ratio, different than the first ratio, that at least partially sets the second trigger level.
9. 9 . The receiver circuit of claim 8 , wherein the first ratio is between approximately 4:1 and approximately 6:1 and the second ratio is between approximately 0.8:1 and approximately 1.2:1.
10. 10 . The receiver circuit of claim 1 , wherein the first and second trigger circuitry comprise respective first and second Schmitt trigger circuits, with the respective first and second trigger levels being configured based at least in part on utilization of different channel sizes for respective corresponding field effect transistors in the first and second Schmitt trigger circuits.
11. 11 . The receiver circuit of claim 1 , further comprising a level shifter coupled between the outputs of the respective first and second trigger circuitry and the output node of the receiver circuit.
12. 12 . The receiver circuit of claim 1 , further comprising a latch circuit coupled between the outputs of the respective first and second trigger circuitry and the output node of the receiver circuit.
13. 13 . The receiver circuit of claim 12 , wherein the latch circuit comprises a serial arrangement of multiple invertors, with an input of a first one of the multiple inverters being coupled to the outputs of the respective first and second trigger circuitry, an output of the first one of the multiple inverters being coupled to an input of another one of the multiple inverters, and an output of the other one of the multiple inverters being coupled to the outputs of the first and second trigger circuitry.
14. 14 . The receiver circuit of claim 12 , wherein an output of the latch circuit is coupled to an input of a level shifter circuit and an output of the level shifter circuit is coupled to the output node of the receiver circuit.
15. 15 . An integrated circuit, comprising: a plurality of receiver circuits; and additional circuitry coupled to the plurality of receiver circuits; wherein at least one of the receiver circuits comprises: first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit; and second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level; wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
16. 16 . The integrated circuit of claim 15 , wherein the first trigger circuitry is configured to drive the output node of the corresponding receiver circuit to one of a logic high level and a logic low level responsive to the low-to-high transition of the input signal and the second trigger circuitry is configured to drive the output node of the corresponding receiver circuit to the other of the logic high level and the logic low level responsive to the high-to-low transition of the input signal.
17. 17 . The integrated circuit of claim 15 , wherein the first and second trigger circuitry comprise respective first and second inverters, each of the first and second inverters having an input coupled to the input node of the corresponding receiver circuit and an output coupled to the output node of the corresponding receiver circuit.
18. 18 . The integrated circuit of claim 17 , wherein channel sizes of respective P-type and N-type field effect transistors of the first inverter are configured in a first ratio that at least partially sets the first trigger level, and channel sizes of respective P-type and N-type field effect transistors of the second inverter are configured in a second ratio, different than the first ratio, that at least partially sets the second trigger level.
19. 19 . A method of manufacturing an integrated circuit, comprising: forming a plurality of receiver circuits; and forming additional circuitry; wherein the receiver circuits are coupled to the additional circuitry; and wherein forming each of one or more of the receiver circuits comprises: forming first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit; forming second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level; wherein respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit.
20. 20 . The method of claim 19 , wherein forming the first trigger circuitry comprises forming respective P-type and N-type field effect transistors of a first inverter of the first trigger circuitry with channel sizes in a first ratio that at least partially sets the first trigger level, and forming the second trigger circuitry comprises forming respective P-type and N-type field effect transistors of a second inverter of the second trigger circuitry with channel sizes in a second ratio, different than the first ratio, that at least partially sets the second trigger level.

Description

TECHNICAL FIELD The present disclosure relates to the field of electronic circuits and systems, and more particularly, but not exclusively, to receiver circuits. BACKGROUND Receiver circuits are illustratively utilized as part of input/output (I/O) circuitry in an integrated circuit, and in numerous other applications. Such receiver circuits in some applications receive input signals from other integrated circuits and/or from other external components of an electronic system. SUMMARY The present disclosure describes receiver circuits with parallel trigger circuitry, as well as integrated circuits containing such receiver circuits, and related methods. This summary is not an extensive overview of the disclosure. Rather, a purpose of the summary is to present some examples of the present disclosure in a simplified form as a prelude to a more detailed description that is presented later. In some examples, a receiver circuit includes first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit, and second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. In some other examples, an integrated circuit comprises a plurality of receiver circuits, and additional circuitry coupled to the plurality of receiver circuits. At least one of the receiver circuits comprises first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit, and second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. In some additional examples, a method of manufacturing an integrated circuit comprises forming a plurality of receiver circuits, and forming additional circuitry, wherein the receiver circuits are coupled to the additional circuitry, and wherein forming each of one or more of the receiver circuits comprises forming first trigger circuitry configured with a first trigger level for a low-to-high transition of an input signal applied to an input node of the receiver circuit, and forming second trigger circuitry arranged at least in part in parallel with the first trigger circuitry and configured with a second trigger level for a high-to-low transition of the input signal, the second trigger level being different than the first trigger level. Respective inputs of the first and second trigger circuitry are coupled to the input node of the receiver circuit, and respective outputs of the first and second trigger circuitry are coupled to an output node of the receiver circuit. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a receiver circuit with parallel trigger circuitry in accordance with examples of the present disclosure; FIG. 2 is a block diagram of an integrated circuit that includes a plurality of receiver circuits and additional circuitry in accordance with examples of the present disclosure; FIG. 3 is a schematic diagram of an implementation of the FIG. 1 receiver circuit in accordance with examples of the present disclosure; FIGS. 4 and 5 are timing diagrams illustrating operation of a receiver circuit with parallel trigger circuitry in accordance with examples of the present disclosure; FIG. 6 shows another receiver circuit with parallel trigger circuitry in accordance with examples of the present disclosure, in which Schmitt trigger circuits are utilized in the parallel trigger circuitry; FIG. 7 is a flow diagram illustrating a method of operating a receiver circuit in accordance with examples of the present disclosure; and FIG. 8 is a flow diagram illustrating a method of manufacturing an integrated circuit comprising a plurality of receiver circuits in accordance with examples of the present disclosure. DETAILED DESCRIPTION The present disclosure is described with reference to the attached figures. The components in the figures are not drawn to scale. Instead, emphasis is placed on clearly illustrating overall features and principles of the present disclosure. Numerous specific details and relationships are set forth with reference to examples of the figures to provide an unders