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US-20260128742-A1 - GATE DRIVER

US20260128742A1US 20260128742 A1US20260128742 A1US 20260128742A1US-20260128742-A1

Abstract

A gate driver includes a first terminal configured to receive a logic signal and a second terminal configured to receive a pulse signal. The gate driver is configured to drive a switch element in response to the pulse signal. At either the rising edge or the falling edge of the pulse signal, if the logic signal is a first logic, the gate driver is configured to increase the gate driving capability of the switch element when turning ON the switch element by one stage, and if the logic signal is a second logic, the gate driver is configured to decrease the gate driving capability when turning ON the switch element by one stage.

Inventors

  • Masahiko ARIMURA

Assignees

  • ROHM CO., LTD.

Dates

Publication Date
20260507
Application Date
20251031
Priority Date
20241107

Claims (11)

  1. 1 . A gate driver comprising: a first terminal configured to receive a logic signal; and a second terminal configured to receive a pulse signal, wherein the gate driver is configured to drive a switch element in response to the pulse signal, and at either a rising edge or a falling edge of the pulse signal, if the logic signal is a first logic, the gate driver is configured to increase the gate driving capability of the switch element when turning ON the switch element by one stage, and if the logic signal is a second logic, the gate driver is configured to decrease the gate driving capability when turning ON the switch element by one stage.
  2. 2 . The gate driver of claim 1 , wherein at the other of the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic, the gate driver is configured to increase the gate driving capability when turning OFF the switch element by one stage, and if the logic signal is the second logic, the gate driver is configured to decrease the gate driving capability when turning OFF the switch element by one stage.
  3. 3 . The gate driver of claim 1 , wherein at the other of the rising edge or the falling edge of the pulse signal, if the logic signal is the second logic, the gate driver is configured to increase the gate driving capability when turning OFF the switch element by one stage, and if the logic signal is the first logic, the gate driver is configured to decrease the gate driving capability when turning OFF the switch element by one stage.
  4. 4 . The gate driver of claim 1 , wherein at either the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic, the gate driver is also configured to increase the gate driving capability of the switch element when turning OFF the switch element by one stage, and if the logic signal is the second logic, the gate driver is also configured to decrease the gate driving capability when turning OFF the switch element by one stage.
  5. 5 . The gate driver of claim 1 , wherein when the gate driving capability is neither at the minimum nor maximum value, at either the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic consecutively for a first predetermined number of times, the gate driver is configured to increase the gate driving capability when turning ON the switch element by one stage, and if the logic signal is the second logic consecutively for a second predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning ON the switch element by one stage.
  6. 6 . The gate driver of claim 2 , wherein when the gate driving capability is neither at the minimum nor maximum value, at either the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic consecutively for a first predetermined number of times, the gate driver is configured to increase the gate driving capability when turning ON the switch element by one stage, and if the logic signal is the second logic consecutively for a second predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning ON the switch element by one stage, and when the gate driving capability is neither at the minimum nor maximum value, at the other of the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic consecutively for a third predetermined number of times, the gate driver is configured to increase the gate driving capability when turning OFF the switch element by one stage, and if the logic signal is the second logic consecutively for a fourth predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning OFF the switch element by one stage.
  7. 7 . The gate driver of claim 3 , wherein when the gate driving capability is neither at the minimum nor maximum value, at either the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic consecutively for a first predetermined number of times, the gate driver is configured to increase the gate driving capability when turning ON the switch element by one stage, and if the logic signal is the second logic consecutively for a second predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning ON the switch element by one stage, and when the gate driving capability is neither at the minimum nor maximum value, at the other of the rising edge or the falling edge of the pulse signal, if the logic signal is the second logic consecutively for a third predetermined number of times, the gate driver is configured to increase the gate driving capability when turning OFF the switch element by one stage, and if the logic signal is the first logic consecutively for a fourth predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning OFF the switch element by one stage.
  8. 8 . The gate driver of claim 4 , wherein when the gate driving capability is neither at the minimum nor maximum value, at either the rising edge or the falling edge of the pulse signal, if the logic signal is the first logic consecutively for a first predetermined number of times, the gate driver is configured to increase the gate driving capability when turning OFF the switch element and the gate driving capability when turning ON the switch element by one stage each, and if the logic signal is the second logic consecutively for a second predetermined number of times, the gate driver is configured to decrease the gate driving capability when turning ON the switch element and the gate driving capability when turning OFF the switch element by one stage each.
  9. 9 . The gate driver of claim 1 , wherein the gate driver is configured to control a gate current of the switch element so that the gate current of the switch element becomes a constant current at each stage of the gate driving capability.
  10. 10 . The gate driver of claim 1 , further comprising: a third terminal configured to receive a reset signal for resetting the gate driving capability to the minimum value, wherein the gate driver is configured, when the reset signal is supplied to the third terminal, to reset the gate driving capability when turning ON the switch element and the gate driving capability when turning OFF the switch element to their respective minimum values.
  11. 11 . The gate driver of claim 1 , further comprising: a fourth terminal configured to receive a set signal for setting the gate driving capability to the maximum value, wherein the gate driver is configured, when the set signal is supplied to the fourth terminal, to set the gate driving capability when turning ON the switch element and the gate driving capability when turning OFF the switch element to their respective maximum values.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present invention claims priority under 35 U.S.C. § 119 Japanese Patent Application No. 2024-195118 filed Nov. 7, 2024, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION 1. Technical Field The present disclosure relates to a gate driver. 2. Description of Related Art Conventionally, gate drivers for driving power devices such as MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors) have been used in various applications. As an example of prior art related to the above, Japanese Patent Application Laid-Open No. 2021-010258 can be cited. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the basic configuration of a signal transmission device. FIG. 2 is a diagram illustrating the basic structure of a transformer chip. FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device shown in FIG. 3. FIG. 5 is a plan view of a layer in the semiconductor device shown in FIG. 3 where low-potential coils are formed. FIG. 6 is a plan view of a layer in the semiconductor device shown in FIG. 3 where high-potential coils are formed. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view (showing a separation structure) of region XIII shown in FIG. 7. FIG. 9 is a diagram schematically showing an example of the layout of a transformer chip. FIG. 10 is a diagram illustrating a comparative example and a first embodiment of a gate driver. FIG. 11 is a diagram illustrating the switching settings for gate driving capability in the comparative example. FIG. 12 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element in the comparative example. FIG. 13 is a diagram illustrating the switching settings for gate driving capability in the first embodiment. FIG. 14 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when increasing the gate driving capability of the switch element in the first embodiment. FIG. 15 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when decreasing the gate driving capability of the switch element in the first embodiment. FIG. 16 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when maintaining the gate driving capability of the switch element at the second level in the first embodiment. FIG. 17 is a diagram illustrating a first modification of the switching settings for gate driving capability in the first embodiment. FIG. 18 is a diagram illustrating a second modification of the switching settings for gate driving capability in the first embodiment. FIG. 19 is a diagram illustrating a second embodiment of the gate driver. FIG. 20 is a diagram illustrating a configuration example of two drivers. FIG. 21 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when increasing the gate driving capability of the switch element in the second embodiment. FIG. 22 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when decreasing the gate driving capability of the switch element in the second embodiment. FIG. 23 is a timing chart illustrating an example of transitions in settings for turning ON and OFF a switch element when maintaining the gate driving capability of the switch element at the second level in the second embodiment. FIG. 24 is a diagram illustrating a third embodiment of the gate driver. DETAILED DESCRIPTION <Signal Transmission Device (Basic Configuration)> FIG. 1 is a diagram illustrating the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (what is generally called an isolated gate driver IC) that, while isolating between a primary circuit system 200p (VCC1-GND1 system) and a secondary circuit system 200s (VCC2-GND2 system), transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s to drive the gate of a switching device (unillustrated) provided in the secondary circuit system 200s. The signal transmission device 200 has, for example, a controller chip 210, a driver chip 220, and a transformer chip 230 sealed in a single package. The controller chip 210 is a semiconductor chip that operates by being supplied with a supply voltage VCC1 (e.g., seven volts at the maximum with respect to GND1). The controller chip 210 has, for example, a pulse transmission circuit 211 and buffers 212 and 213 integrated in it. The pulse transmission circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 according to