US-20260128744-A1 - APPARATUS AND METHODS FOR NONLINEARITY CANCELLATION IN ELECTRONIC SYSTEMS

Abstract

Apparatus and methods for nonlinearity cancellation in electronic systems are disclosed. In certain embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel and that each include at least one instantiation of a circuit that behaves nonlinearly. Thus, the nonlinear circuit is replicated and included at least once in each circuit channel. Each of the circuit channels has an input scaling factor and an output scaling factor that can vary from one circuit channel to another. The output signals from the circuit channels after scaling are combined to generate a combined output signal. The input and output scaling factors are selected to cancel or reduce nonlinearities.

Inventors

• Cristian Enrique Alvarez Fontecilla
• Peter DELOS

Assignees

• Analog Devices International Unlimited Company

Dates

Publication Date

20260507

Application Date

20241106

Claims (20)

1. 1 . An electronic system comprising: two or more circuit channels configured to process an input signal in parallel to generate two or more output signals, wherein the two or more circuit channels comprise: a first circuit channel including a first circuit block configured to receive the input signal scaled by a first input scaling factor, the first circuit channel configured to generate a first output signal based on scaling an output of the first circuit block by a first output scaling factor; and a second circuit channel including a second circuit block configured to receive the input signal scaled by a second input scaling factor, the second circuit channel configured to generate a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have a nonlinearity; and an output combiner configured to combine the two or more output signals including the first output signal and the second output signal to generate a combined output signal in which the nonlinearity is canceled.
2. 2 . The electronic system of claim 1 , wherein the two or more circuit channels further comprise: a third circuit channel including a third circuit block configured to receive the input signal scaled by a third input scaling factor, the third circuit channel configured to generate a third output signal of the two or more output signals based on scaling an output of the third circuit block by a third output scaling factor.
3. 3 . The electronic system of claim 1 , wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.
4. 4 . The electronic system of claim 3 , wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.
5. 5 . The electronic system of claim 1 , wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.
6. 6 . The electronic system of claim 1 , wherein the nonlinearity is a harmonic distortion component.
7. 7 . The electronic system of claim 1 , further comprising a calibration circuit configured to calibrate the first output scaling factor based on a detected value of the first input scaling factor, and to calibrate the second output scaling factor based on a detected value of the second input scaling factor.
8. 8 . The electronic system of claim 1 , wherein the second circuit channel further includes one or more additional circuit blocks in parallel with the second circuit block, each of the one or more additional circuit blocks receiving the input signal scaled by the second input scaling factor.
9. 9 . The electronic system of claim 8 , wherein the second circuit channel is further configured to generate the second output signal based on combining an output of each of the one or more additional circuit blocks with the output of the second circuit block.
10. 10 . The electronic system of claim 1 , wherein the second circuit block is a replica of the first circuit block.
11. 11 . The electronic system of claim 1 , implemented in a phased array antenna.
12. 12 . A method of nonlinearity cancellation, the method comprising: processing an input signal in parallel using two or more circuit channels to generate two or more output signals, wherein processing the input signal includes: scaling the input signal by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel; generating a first output signal based on scaling an output of the first circuit block by a first output scaling factor; scaling the input signal by a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit channel; generating a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have a nonlinearity; and combining the two or more output signals including the first output signal and the second output signal using an output combiner to generate a combined output signal in which the nonlinearity is canceled.
13. 13 . The method of claim 12 , further comprising: scaling the input signal by a third input scaling factor to generate a third scaled input signal for a third circuit block of a third circuit channel; and generating a third output signal of the two or more output signals based on scaling an output of the third circuit block by a third output scaling factor.
14. 14 . The method of claim 12 , wherein the first circuit block is a first analog-to-digital converter (ADC) and the second circuit block is a second ADC.
15. 15 . The method of claim 14 , wherein the input signal is an analog or radio frequency signal and the output signal is a digital signal.
16. 16 . The method of claim 12 , wherein a plurality of input scaling factors including the first input scaling factor and the second input scaling factor define a matrix, and wherein a plurality of output scaling factors including the first output scaling factor and the second output scaling factor are based on an inverse of the matrix.
17. 17 . The method of claim 12 , wherein the nonlinearity is a harmonic distortion component.
18. 18 . The method of claim 12 , further comprising calibrating the first output scaling factor based on a detected value of the first input scaling factor and calibrating the second output scaling factor based on a detected value of the second input scaling factor.
19. 19 . The method of claim 12 , wherein the second circuit channel further includes one or more additional circuit blocks in parallel with the second circuit block, the method further comprising providing each of the one or more additional circuit blocks the input signal scaled by the second input scaling factor, and generating the second output signal based on combining an output of each of the one or more additional circuit blocks with the output of the second circuit block.
20. 20 . The method of claim 12 , wherein the second circuit block is a replica of the first circuit block.

Description

FIELD OF THE DISCLOSURE The disclosed technology relates generally to electronics, and more particularly to nonlinearity cancellation of circuit blocks. BACKGROUND Certain electrical circuits are desired to operate linearly, such that an output signal changes in a linear relationship with respect to an applied input signal. However, various nonidealities can result in the output signal exhibiting a nonlinear relationship with respect to the applied input signal. Such nonlinear behavior can arise from a wide variety of sources including, but not limited to, component mismatch, process variation, supply voltage constraints, changing temperature, signal amplitude saturation, and/or various other sources. SUMMARY OF THE DISCLOSURE Apparatus and methods for nonlinearity cancellation in electronic systems are disclosed. In certain embodiments, an electronic system includes two or more circuit channels that process a common input signal in parallel and that each include at least one instantiation of a circuit that behaves nonlinearly. Thus, the nonlinear circuit is replicated and included at least once in each circuit channel. Each of the circuit channels has an input scaling factor and an output scaling factor that can vary from one circuit channel to another. The output signals from the circuit channels after scaling are combined to generate a combined output signal. The input and output scaling factors are selected to cancel or reduce nonlinearities. Accordingly, by selecting suitable values of the input scaling factors and output scaling factors, nonlinear cancellation can be achieved. For example, the teachings herein can be used to cancel or reduce various nonlinearities including, but not limited to, third-order harmonic distortion. In contrast to calibration schemes which suffer from additive sequences and/or a convergence delay, the nonlinearity cancellation schemes herein can have relatively low complexity and/or high speed. The nonlinearity cancellation techniques can be applied to a wide variety of electronic systems, including, for example, data conversion systems and phased array antenna systems. In one aspect, an electronic system includes two or more circuit channels configured to process an input signal in parallel to generate two or more output signals. The two or more circuit channels include a first circuit channel including a first circuit block configured to receive the input signal scaled by a first input scaling factor, the first circuit channel configured to generate a first output signal based on scaling an output of the first circuit block by a first output scaling factor. The two or more circuit channels further include a second circuit channel including a second circuit block configured to receive the input signal scaled by a second input scaling factor, the second circuit channel configured to generate a second output signal based on scaling an output of the second circuit block by a second output scaling factor, wherein the first circuit block and the second circuit block have a nonlinearity. The electronic system further includes an output combiner configured to combine the two or more output signals including the first output signal and the second output signal to generate a combined output signal in which the nonlinearity is canceled. In another aspect, a method of nonlinearity cancellation includes processing an input signal in parallel using two or more circuit channels to generate two or more output signals. Processing the input signal includes scaling the input signal by a first input scaling factor to generate a first scaled input signal for a first circuit block of a first circuit channel, generating a first output signal based on scaling an output of the first circuit block by a first output scaling factor, scaling the input signal by a second input scaling factor to generate a second scaled input signal for a second circuit block of a second circuit channel, and generating a second output signal based on scaling an output of the second circuit block by a second output scaling factor. The first circuit block and the second circuit block have a nonlinearity, and the method further includes combining the two or more output signals including the first output signal and the second output signal using an output combiner to generate a combined output signal in which the nonlinearity is canceled. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of an electronic system according to one embodiment. FIG. 1B is a schematic diagram of an electronic system according to another embodiment. FIG. 2 is a schematic diagram of a data conversion system according to one embodiment. FIG. 3A is a schematic diagram of a data conversion system according to another embodiment. FIG. 3B is a schematic diagram of a data conversion system according to another embodiment. FIG. 4 is a schematic diagram of an electronic system according to another embodiment. FIG. 5A is a schematic diagram