US-20260128748-A1 - HIGH-SPEED DIGITAL TO ANALOG CONVERTER WITH HIGH-SPEED INTERLEAVER AND MISALIGNMENT DETECTOR

US20260128748A1US 20260128748 A1US20260128748 A1US 20260128748A1US-20260128748-A1

Abstract

Described is a high-speed digital-to-analog converter (DAC) with an interleaver and misalignment detector. The interleaver has a first pair of differential pair ports to receive a first data stream from a first sub-DAC and a second pair of differential pair ports to receive a second data stream from a second sub-DAC. Each of the first and second pair of differential pair ports are alternately selected or alternately selected identically clocked by a differential sampling frequency (F S )/2 (F S /2) frequency clock to generate output signals. A set of transmission wires combine certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal. A first transmission wire and a second transmission wire have a defined degree of crossover to reduce differential F S /2 frequency clock feedthrough with minimal change on a device output signal.

Inventors

Jerry Yee-Tung Lam
Douglas Stuart McPherson
Yuriy Greshishchev

Assignees

CIENA CORPORATION

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A device, comprising: an interleaver with a first pair of differential pair ports configured to receive a first data stream from a first sub-digital-to-analog converter (sub-DAC) and a second pair of differential pair ports configured to receive a second data stream from a second sub-DAC, wherein each of the first pair of differential pair ports and each of the second pair of differential pair ports are alternately selected by a differential sampling frequency (F S )/2 (F S /2) frequency clock to generate output signals; a set of transmission wires configured to combine certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal; and a pair of transmission wires configured to output the device output signal, wherein a first transmission wire and a second transmission wire of the pair of transmission wires have a defined degree of crossover to reduce differential F S /2 frequency clock feedthrough on the device output signal.
2 . The device of claim 1 , further comprises a misalignment detector with a replica interleaver and a multiplexor circuit; the replica interleaver including a first replica pair of differential pair ports configured to receive a first replica data stream from the first sub-DAC and a second replica pair of differential pair ports configured to receive a second replica data stream from the second sub-DAC, wherein each of the first replica pair of differential pair ports and each of the second pair of differential pair ports are alternately selected by the differential F S /2 frequency clock to generate replica output signals and replica select signals, and wherein the first replica data stream is based on a first sub-DAC differential F S /4 frequency clock and the second replica data stream is based on a second sub-DAC differential F S /4 frequency clock; and the multiplexor circuit configured to combine certain of the replica output signals and certain of the replica select signals from the first replica pair of differential pair ports and the second replica pair of differential pair ports to generate an alignment signal, wherein the alignment signal is used to align the first sub-DAC F S /4 frequency clock and the second sub-DAC differential F S /4 frequency clock with the differential F S /2 frequency clock.
3 . The device of claim 2 , wherein each replica select signal has a first lobe and a second lobe, and the multiplexor circuit is configured to sum amplitudes of the first lobes and to sum amplitudes of the second lobes to generate the alignment signal.
4 . The device of claim 2 , wherein each replica select signal has an early lobe and a late lobe and the multiplexor circuit is configured to sum amplitudes of the early lobes and to sum amplitudes of the late lobes, and wherein the multiplexor circuit further comprises a comparator configured to compare the sum of the early lobes to the sum of the late lobes to determine the alignment signal.
5 . The device of claim 4 , wherein a comparison indicates a presence, a direction, and a magnitude of the alignment signal.
6 . The device of claim 2 , wherein replica outputs of the first replica pair of differential pair ports and the second pair of differential pair ports are connected to resistors configured to convert some of the replica output signals from a current to a voltage.
7 . The device of claim 1 , wherein the defined degree of crossover adjusts frequency dependent even/odd mode coupling at or in the pair of transmission wires.
8 . The device of claim 1 , wherein the defined degree of crossover adjusts frequency dependent mixed mode coupling at or in the pair of transmission wires.
9 . The device of claim 1 , wherein the defined degree of crossover is adjusted by adjusting a distance between the pair of transmission wires.
10 . A method, comprising: receiving, at a first pair of differential pair ports of an interleaver, a first data stream from a first sub-digital-to-analog converter (sub-DAC); receiving, at a second pair of differential pair ports of the interleaver, a second data stream from a second sub-DAC; alternately selecting each of the first pair of differential pair ports and each of the second pair of differential pair ports by a differential sampling frequency (F S )/2 (F S /2) frequency clock to generate output signals; combining, using a set of transmission wires, certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal; and outputting, using a first transmission wire and a second transmission wire with a defined degree of crossover to reduce differential F S /2 frequency clock feedthrough at a device output, the device output signal.
11 . The method of claim 10 , further comprises receiving, at a first replica pair of differential pair ports of a replica interleaver, a first replica data stream from the first sub-DAC, wherein the first replica data stream is based on a first sub-DAC differential F S /4 frequency clock; receiving, at a second replica pair of differential pair ports of the replica interleaver, a second replica data stream from the second sub-DAC, wherein the second replica data stream is based on a second sub-DAC differential F S /4 frequency clock; alternately selecting each of the first replica pair of differential pair ports and each of the second replica pair of differential pair ports by the differential sampling F S /2 frequency clock to generate replica output signals and replica select signals; and combining, at a multiplexor circuit, certain of the replica output signals and certain of the replica select signals from the first replica pair of differential pair ports and the second replica pair of differential pair ports to generate an alignment signal, wherein the alignment signal is used to align the first sub-DAC F S /4 frequency clock and the second sub-DAC differential F S /4 frequency clock with the differential F S /2 frequency clock.
12 . The method of claim 11 , wherein each replica select signal has a first lobe and a second lobe, and the method further comprises summing amplitudes of the first lobes and summing amplitudes of the second lobes to generate the alignment signal.
13 . The method of claim 11 , wherein each replica select signal has an early lobe and a late lobe and the method further comprises summing amplitudes of the early lobes and summing amplitudes of the late lobes; and comparing a sum of the early lobes to a sum of the late lobes to determine the alignment signal.
14 . The method of claim 13 , wherein a comparison indicates a presence, a direction, and a magnitude the alignment signal.
15 . The method of claim 11 , further comprises converting some of the replica output signals of the first replica pair of differential pair ports and the second pair of differential pair ports from a current to a voltage using resistors.
16 . The method of claim 10 , wherein the defined degree of crossover adjusts frequency dependent even/odd mode coupling at or in the pair of transmission wires.
17 . The method of claim 10 , wherein the defined degree of crossover adjusts frequency dependent mixed mode coupling at or in the pair of transmission wires.
18 . The method of claim 10 , further comprises adjusting the defined degree of crossover by adjusting a distance between the pair of transmission wires.
19 . A device, comprising: an interleaver configured to receive a first data stream from a first sub-digital-to-analog converter (sub-DAC) and a second data stream from a second sub-DAC, and operate using a first clock, wherein each of the first sub-DAC and the second sub-DAC are configured to use a second clock; a replica interleaver configured to receive a first replica data stream from the first sub-DAC and a second replica data stream from the second sub-DAC, and operate at the second clock to generate replica output signals and replica select signals; and a multiplexor circuit configured to combine certain of the replica output signals and certain of the replica select signals to generate an alignment signal, wherein the alignment signal is used to align the second clock with the first clock.
20 . The device of claim 19 , wherein each replica select signal has an early lobe and a late lobe and further comprises the multiplexor circuit configured to sum amplitudes of the early lobes and to sum amplitudes of the late lobes; and a comparator configured to compare the sum of the early lobes to the sum of the late lobes to determine the alignment signal, wherein a comparison indicates a presence, a direction, and a magnitude the alignment signal.

Description

TECHNICAL FIELD This disclosure relates to digital to analog converter (DAC) circuits. BACKGROUND The need for high-speed and high-performance DACs in optical transceivers grows as the data rate in optical coherent modems increases. High-speed and high-performance DACs require multiple high speed multiplexing stages to convert a wide bus of parallel input data into a single high speed analog signal. However, the capacity of semiconductor technologies optimized for high-speed digital signal processing and data processing is lacking in terms of speed of operation, precision in timing, output linearity, and frequency response. Moreover, even if the technology is capable, the circuitry can be complex, occupy a larger portion of area, and have high power consumption. SUMMARY Described herein are apparatus and methods for digital to analog converter (DAC) circuits. In an implementation, a device includes an interleaver with a first pair of differential pair ports configured to receive a first data stream or analog signal from a first sub-digital-to-analog converter (sub-DAC) and a second pair of differential pair ports configured to receive a second data stream or analog signal from a second sub-DAC. Each of the first pair of differential pair ports and each of the second pair of differential pair ports are alternately selected and/or alternately selected identically by a differential sampling frequency (FS)/2 (FS/2) frequency clock to generate output signals. A set of transmission wires are configured to combine certain output signals from the first pair of differential pair ports with certain output signals from the second pair of differential pair ports to generate a device output signal. A pair of transmission wires are configured to output the device output signal. A first transmission wire and a second transmission wire of the pair of transmission wires have a defined degree of crossover to reduce differential FS/2 frequency clock feedthrough on the device output signal with minimal change to the device output signal. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features of the drawings are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. FIG. 1 is a block diagram of an example of a digital to analog converter (DAC) in accordance with embodiments of this disclosure. FIG. 2 is a block diagram of a misalignment detector in accordance with embodiments of this disclosure. FIG. 3 is a diagram of FS/2 frequency clock in alignment with sub-DAC replica data streams or FS/4 frequency clocks in accordance with embodiments of this disclosure. FIG. 4 is a diagram of an early FS/4 frequency clock with respect to a FS/2 frequency clock in accordance with embodiments of this disclosure. FIG. 5 is a diagram of a late FS/4 frequency clock with respect to a FS/2 frequency clock in accordance with embodiments of this disclosure. FIG. 6 is a block diagram of an interleaver in accordance with embodiments of this disclosure. FIG. 7 is a block diagram of a misalignment detector circuit in accordance with embodiments of this disclosure. FIG. 8 is a flowchart of an example technique for digital to analog conversion in accordance with embodiments of this disclosure. DETAILED DESCRIPTION Reference will now be made in greater detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings and the description to refer to the same or like parts. As used herein, the terminology “computer” or “computing device” includes any unit, or combination of units, capable of performing any method, or any portion or portions thereof, disclosed herein. The computer or computing device may include a processor. As used herein, the terminology “processor” indicates one or more processors, such as one or more special purpose processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more application processors, one or more central processing units (CPU) s, one or more graphics processing units (GPU) s, one or more digital signal processors (DSP) s, one or more application specific integrated circuits (ASIC) s, one or more application specific standard products, one or more field programmable gate arrays, any other type or combination of integrated circuits, one or more state machines, or any combination thereof. As used herein, the terminology “memory” indicates any computer-usable or computer-readable medium or device that can tangibly contain, store, communicate, or transport any signal or information that may be used by or in connection with any processor. For example, a memory may be one or more r