US-20260128792-A1 - SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM

US20260128792A1US 20260128792 A1US20260128792 A1US 20260128792A1US-20260128792-A1

Abstract

A signal processing device includes a supply unit that supplies identical clocks to a plurality of ADCs in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplies non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other, and an average value output unit that outputs an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputs an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other.

Inventors

Hironori Nakanishi

Assignees

NEC CORPORATION

Dates

Publication Date: 20260507
Application Date: 20251015
Priority Date: 20241107

Claims (10)

1 . A signal processing device comprising: a supply circuit that supplies identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplies non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and an average value output circuit that outputs an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputs an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other.
2 . The signal processing device according to claim 1 , wherein the signal processing device includes an addition circuit that calculates a sum of the first average values of the plurality of ADCs, and a bit shift operation circuit that divides the sum by a number of the plurality of ADCs.
3 . The signal processing device according to claim 1 , wherein the plurality of ADCs includes a first ADC and a second ADC, the supply circuit supplies a first clock to the first ADC, the signal processing device includes a phase shift circuit that outputs a second clock having a phase different from a phase of the first clock by 180°, and the supply circuit supplies the first clock to the second ADC in a case where the plurality of signals are not identical to each other, and supplies the second clock to the second ADC in a case where the plurality of signals are identical to each other.
4 . The signal processing device according to claim 3 , wherein each of the plurality of signals that are not identical to each other is transmitted via a plurality of channels of a first optical fiber, and the plurality of signals identical to each other is obtained by splitting a signal transmitted via one channel of a second optical fiber.
5 . The signal processing device according to claim 4 , wherein each of the plurality of channels of the first optical fiber is relevant to a plurality of cores of a multi core fiber (MCF), and the one channel of the second optical fiber is relevant to one core of a single core fiber (SCF).
6 . The signal processing device according to claim 5 , comprising: a splitter; and an analog switch, wherein the splitter splits a signal transmitted via a first core of the MCF or a first core of the SCF, one of the signals split by the splitter is input to the first ADC, and the analog switch outputs another one of the signals split by the splitter to the second ADC in a case where the splitter splits the signal transmitted via the first core of the SCF, and outputs a signal transmitted via a second core of the MCF to the second ADC in a case where the splitter splits the signal transmitted via the first core of the MCF.
7 . The signal processing device according to claim 2 , comprising an average value calculation circuit that calculates the first average value, wherein in a case where the plurality of signals are not identical to each other, m (m is an integer of 2 or more) digital values are input to the average value calculation circuit per cycle, and in a case where the plurality of signals are identical to each other, n (n is an integer of 2 or more) digital values are input to the average value calculation circuit per cycle, m is an integer multiple of n, m/n is relevant to a number of the ADCs, and the average value calculation circuit includes a selection circuit that selects either an average value of the m digital values or an average value of the n digital values as the first average value.
8 . The signal processing device according to claim 1 , comprising an offset adjustment circuit that subtracts the first average value or the second average value from each of the plurality of digital values output from one of the ADCs.
9 . A signal processing method comprising: supplying identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplying non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and outputting an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputting an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other.
10 . A non-transitory computer-readable medium storing a program for causing a computer to execute: a process of supplying identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplying non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and a process of outputting an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputting an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other.

Description

INCORPORATION BY REFERENCE This application is based upon and claims the benefit of priority from Japanese patent application No. 2024-194857, filed on November 7, 2024, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD The present disclosure relates to a signal processing device, a signal processing method, and a program. BACKGROUND ART WO 2024/135107 A1 discloses a technique for reducing crosstalk between cores of an optical fiber by using a multiple-input multiple-output (MIMO) technique. SUMMARY The MIMO preprocessing includes average value calculation processing of calculating an average value of data received via an optical fiber for each channel. In a case where the number of channels of a second optical fiber is smaller than the number of channels of a first optical fiber and the average value calculation units as many as the number of channels of the first optical fiber are used, the throughput of the average value calculation processing of data transmitted via the second optical fiber decreases. The present disclosure has been made to solve such a problem, and an example object thereof is to provide a signal processing device, a signal processing method, and a program that suppress a decrease in throughput in average value calculation processing of calculating an average value of data transmitted by an optical fiber for each channel. A signal processing device according to an example aspect of the present disclosure includes: a supply unit that supplies identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplies non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and an average value output unit that outputs an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputs an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other. A signal processing method according to an example aspect of the present disclosure includes: supplying identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplying non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and outputting an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputting an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other. A program according to an example aspect of the present disclosure causes a computer to execute: a process of supplying identical clocks to a plurality of analog-to-digital converters (ADCs) in a case where a plurality of signals input to the plurality of ADCs are not identical to each other, and supplying non-identical clocks to the plurality of ADCs in a case where the plurality of signals are identical to each other; and a process of outputting an average value of a plurality of digital values output from one ADC that is each of a plurality of the ADCs as a first average value in a case where the plurality of signals are not identical to each other, and outputting an average value of the first average values in the plurality of the ADCs as a second average value in a case where the plurality of signals are identical to each other. According to the present disclosure, it is possible to provide a signal processing device, a signal processing method, and a program that suppress a decrease in throughput in average value calculation processing of calculating an average value of data transmitted by an optical fiber for each channel. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a diagram for explaining an example of processing on data transmitted via an MCF; FIG. 2 is a diagram for explaining an example of processing on data transmitted via an SCF; FIG. 3 is a block diagram illustrating a configuration of a signal processing device according to the present disclosure; FIG. 4 is a flowchart illustrating a signal processing method according to the present disclosure; FIG. 5 is a block diagram illustrating a configuration of the signal processing device according to the present disclosure; FIG. 6 is a diagram for explaining the operation of a MIMO preprocessing circuit according to the present disclosure; FIG. 7 is a block diagram illustrating a configuration of the signal processing device