US-20260128850-A1 - MEMORY SYSTEMS, SYSTEMS AND OPERATING METHODS THEREOF, COMPUTER-READABLE STORAGE MEDIUMS

US20260128850A1US 20260128850 A1US20260128850 A1US 20260128850A1US-20260128850-A1

Abstract

The present disclosure provides example memory systems and operating methods thereof, systems and operating methods thereof, and computer-readable storage mediums. An example memory system includes an interface and an interface controller, the interface is connected to a host through a link; the interface controller is configured to: determine whether link equalization is to be redone based on a temperature change of the memory system and error counts of the interface; the error counts include a first error count and a second error count, and the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state; in response to the link equalization being to be redone, trigger the link equalization.

Inventors

Lingjun Qin

Assignees

YANGTZE MEMORY TECHNOLOGIES CO., LTD

Dates

Publication Date: 20260507
Application Date: 20260105
Priority Date: 20230914

Claims (20)

1 . A memory system, comprising: an interface connected to a host through a link; and an interface controller, configured to: determine whether a link equalization is to be redone based on a temperature change of the memory system and error counts of the interface, wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state; and in response to the link equalization being to be redone, trigger the link equalization.
2 . The memory system of claim 1 , wherein the interface controller is configured to: obtain current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time; in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtain the first error count and the second error count; and in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determine that the link equalization is to be redone.
3 . The memory system of claim 2 , wherein the interface controller is further configured to: in response to a transmission rate of the link being greater than or equal to 8 GT/s, set the first error count and the second error count to zero, and start a timer; and obtain the current temperature of the memory system each time the timing of the timer reaches a timing period.
4 . The memory system of claim 2 , wherein the interface controller is further configured to: set the first error count and the second error count to zero after the link equalization is successful.
5 . The memory system of claim 1 , wherein the interface controller is further configured to: request a transmission at the interface to be suspended and wait for the interface to enter an idle state before triggering the link equalization; and set a flag indicating performing equalization in a control register of the interface after the interface enters the idle state.
6 . The memory system of claim 5 , wherein the interface is configured to: in response to the flag indicating performing equalization, perform the link equalization, which includes sending a training sequence to the host, to notify the host to perform the link equalization.
7 . The memory system of claim 1 , wherein the memory system further includes a memory device and a memory controller coupled to the memory device and configured to control the memory device; wherein: the memory controller includes the interface and the interface controller, or the memory controller includes the interface, and the interface controller is external to the memory controller.
8 . The memory system of claim 1 , wherein the interface includes an interface of high-speed serial computer expansion bus standard.
9 . A computer-readable storage medium, wherein the computer-readable storage medium stores computer program that when executed, may implement a method for operating a memory system, comprising: determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface; wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state; and in response to the link equalization being to be redone, triggering the link equalization.
10 . The computer-readable storage medium of claim 9 , wherein the determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface includes: obtaining current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time; in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtaining the first error count and the second error count; and in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determining that the link equalization is to be redone.
11 . The computer-readable storage medium of claim 10 , wherein the method for operating the memory system further includes: in response to a transmission rate of a link being greater than or equal to 8 GT/s, setting the first error count and the second error count to zero, and starting a timer; and obtaining the current temperature of the memory system each time the timing of the timer reaches a timing period.
12 . The computer-readable storage medium of claim 10 , wherein the method for operating the memory system further includes: setting the first error count and the second error count to zero after the link equalization is successful.
13 . The computer-readable storage medium of claim 9 , wherein the method for operating the memory system further includes: requesting a transmission at the interface to be suspended and waiting for the interface to enter an idle state before triggering the link equalization; wherein the triggering the link equalization includes setting a flag indicating performing equalization in a control register of the interface after the interface enters the idle state.
14 . The computer-readable storage medium of claim 13 , wherein the method for operating the memory system further includes: in response to the flag indicating performing equalization, performing the link equalization, which includes sending a training sequence to a host, to notify the host to perform the link equalization.
15 . A method of operating a memory system, comprising: determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface, wherein the error counts include a first error count and a second error count, the first error count is a number of recoverable errors in data packets received by the interface, and the second error count is a number of times that the interface switches between a normal operating state and a recovery state; and in response to the link equalization being to be redone, triggering the link equalization.
16 . The method of claim 15 , wherein the determining whether a link equalization is to be redone based on a temperature change of the memory system and error counts of an interface includes: obtaining current temperature of the memory system and a temperature of the memory system at which the link equalization was performed last time, in response to an absolute value of a difference between the current temperature and the temperature of the memory system at which the link equalization was performed last time being greater than a first preset value, obtaining the first error count and the second error count; and in response to the first error count being greater than a second preset value or the second error count being greater than a third preset value, determining that the link equalization is to be redone.
17 . The method of claim 16 , further including: in response to a transmission rate of a link being greater than or equal to 8 GT/s, setting the first error count and the second error count to zero, and starting a timer; and obtaining the current temperature of the memory system each time the timing of the timer reaches a timing period.
18 . The method of claim 16 , further including: setting the first error count and the second error count to zero after the link equalization is successful.
19 . The method of claim 15 , further including: requesting a transmission at the interface to be suspended and waiting for the interface to enter an idle state before triggering the link equalization; wherein the triggering the link equalization includes setting a flag indicating performing equalization in a control register of the interface after the interface enters the idle state.
20 . The method of claim 19 , further including: in response to the flag indicating performing equalization, performing the link equalization, which includes sending a training sequence to a host, to notify the host to perform the link equalization.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present application is a continuation of U.S. application Ser. No. 18/404,670, filed on Jan. 4, 2024, which claims the benefit of priority to China Application No. 202311190444.1, filed on Sep. 14, 2023, the content of which is incorporated herein by reference in its entirety. FIELD OF TECHNOLOGY The present disclosure relates to the field of semiconductor technology, and in examples to a memory system and operating method thereof, a system and operating method thereof, and computer-readable storage medium. BACKGROUND In a system including a host and a memory system, the host and the memory system communicate according to a communication protocol, the host and the memory system are connected through a link, and the two ends of the link are the interface at the side of the host and the interface at the side of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of an example system having a memory system provided by an example of the present disclosure. FIG. 2 is a schematic diagram of an example memory card having a memory system provided by an example of the present disclosure. FIG. 3 is a schematic diagram of an example solid state drive having a memory system provided by an example of the present disclosure. FIG. 4 is a schematic diagram of an example memory device including a peripheral circuit provided by an example of the present disclosure. FIG. 5 is a schematic cross-sectional view of a memory array including memory strings provided by an example of the present disclosure. FIG. 6 is a schematic diagram of an example memory device including a memory array and peripheral circuits provided by an example of the present disclosure. FIG. 7 is a schematic diagram of a system including an interface and a host interface provided by an example of the present disclosure. FIG. 8 is a schematic flowchart of an implementation of a method for operating a memory system provided by an example of the present disclosure. FIG. 9 is a schematic diagram of the framework flow of the method for operating a memory system provided by an example of the present disclosure. FIG. 10 is another schematic diagram of the framework flow of the method for operating a memory system provided by an example of the present disclosure. FIG. 11 is a partial schematic diagram of a memory system including an interface and an interface controller provided by an example of the present disclosure. FIG. 12 is a schematic flowchart of an implementation of a method for operating a system provided by an example of the present disclosure. DETAILED DESCRIPTION Examples of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although example implementations of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the implementations set forth herein. Rather, these examples are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. In the following description, numerous specific details are given in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, not all features of the actual example are described here, and well-known functions and structures are not described in detail. In the appended drawings, like reference numerals refer to like elements throughout. It should be understood that the spatially relative terms such as “beneath”, “below”, “lower”, “under”, “above”, “on”, etc., may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the appended drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operations in addition to the orientation depicted in the figures. For example, if the device in the appended drawings is turned over, an element or a feature described as “below” or “beneath” or “under” another element or feature would then be oriented “above” the another element or feature. Thus, example terms “below” and “under” may encompass both directions of up and down. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially descriptive terms used herein should be interpreted accordingly. A term used herein is for the purpose of describing a particular example only and is not to be considered as limitation of the present disclosure. As used herein, the singular forms “a”, “an”