US-20260128853-A1 - METHODS AND SYSTEMS FOR ADJUSTING DIFFERENTIAL CLOCK SIGNALS

US20260128853A1US 20260128853 A1US20260128853 A1US 20260128853A1US-20260128853-A1

Abstract

The present invention is directed to electrical circuits. In an embodiment, the present invention provides a clock compensation device configured to correct timing discrepancies in differential clock signals. The circuit comprises positive and negative lines with multiple inverters, including crossover inverters that generate correction signals to maintain synchronization between the clock signals. There are other embodiments as well.

Inventors

Hemesh Yasotharan
Parmanand Mishra

Assignees

CELESTIAL AI INC.

Dates

Publication Date: 20260507
Application Date: 20241101

Claims (20)

1 . A circuit comprising: a differential input comprising a positive input and a negative input, the different input being configured to receive different clock signals, the differential clock signals comprising a positive clock signal and a negative clock signal; a differential output comprising a positive output and a negative output; a positive line coupled to the positive input and the positive output, the positive line comprising a first positive inverter and a second positive inverter; a negative line coupled to the negative input and the negative output, the negative line comprising a first negative inverter and a second negative inverter; and a first crossover inverter directed coupled to the positive line and the second negative inverter at a first node, the first crossover inverter being characterized by a first delay, the first crossover inverter being configured to provide a positive correction signal based on the positive clock signal with the first delay to the first node.
2 . The circuit of claim 1 , further comprising: a third positive inverter directly coupled to the first positive inverter and the second positive inverter; a third negative inverter directly coupled to the first negative inverter and the second negative inverter; and a second crossover inverter coupled to the negative input and a node between the second positive inverter and the third positive inverter.
3 . The circuit of claim 1 , further comprising a controller coupled to the negative output, the controller being configured to provide a control signal disengage the first crossover inverter based at least on the negative output.
4 . The circuit of claim 3 , further comprising a switch configured to disengage the first crossover inverter in response to the control signal.
5 . The circuit of claim 3 , further comprising a matrix bus for coupling crossover inverters to the positive line and the negative line.
6 . The circuit of claim 3 , wherein the controller is configured on a feedback path.
7 . The circuit of claim 1 , wherein the positive correction signal comprises the first delay and a second delay the first positive inverter.
8 . The circuit of claim 1 , further comprising a second crossover inverter directed coupled to the negative line and the second positive inverter at a second node, the second crossover inverter being characterized by a second delay, the first crossover inverter being configured to provide a positive negative signal based on the negative clock signal with the second delay to the first node.
9 . A clock compensation device, comprising a differential input comprising a positive input and a negative input, the differential input being configured to receive differential clock signals, the differential clock signals comprising a positive clock signal and a negative clock signal; a differential output comprising a positive output and a negative output; a positive line coupled to the positive input and the positive output, the positive line comprising a first positive inverter and a second positive inverter; a negative line coupled to the negative input and the negative output, the negative line comprising a first negative inverter and a second negative inverter; a controller coupled to the differential output, the controller being configured to provide a control signal based at least on the differential output; and a crossover section coupled to the controller, the crossover section comprising a first crossover inverter, the crossover section being configured to provide a first correction signal by connecting a first node on the positive line to a second node on the negative line via the first crossover inverter.
10 . The device of claim 9 , further comprising a feedback path comprising the differential output and the controller, the feedback path being configured to provide feedback signals indicative of a designed adjustment for the positive output and the negative output.
11 . The device of claim 9 , wherein the controller is configured to adjust operation of the crossover section based on a difference between the positive output and the negative output.
12 . The device of claim 9 , wherein the crossover section further comprising a second crossover inverter, the crossover section being configured to provide a first correction signal by connecting a third node on the negative line to a fourth node on the positive line via the second crossover inverter.
13 . The device of claim 9 , wherein the crossover section further a matrix bus and a plurality of switches for selecting the first node and the second for generating the first correction signal.
14 . The device of claim 9 , wherein the controller is configured to determine a connection of the first crossover inverter based on a desired adjustment and a delay associated with the first crossover inverter.
15 . A driver circuit comprising: a differential input comprising a positive input and a negative input, the differential input being configured to receive differential clock signals, the differential clock signals comprising a positive clock signal and a negative clock signal; a differential output comprising a positive output and a negative output; a positive line coupled to the positive input and the positive output, the positive line comprising a first positive inverter and a second positive inverter; a negative line coupled to the negative input and the negative output, the negative line comprising a first negative inverter and a second negative inverter; a first crossover inverter directly coupled to the positive line and the second negative inverter at a first node, the first crossover inverter being characterized by a first delay, the first crossover inverter being configured to provide a positive correction signal based on the positive clock signal with the first delay to the first node; and a multiplexer (MUX) configured to receive the corrected differential clock signals from the differential output, the MUX being configured to select one of multiple input data signals based on the timing of the corrected differential clock signals.
16 . The driver circuit of claim 15 , further comprising a clock generation circuit coupled to the differential input, the clock generation circuit being configured to generate the differential clock signals with a frequency and phase for the MUX.
17 . The driver circuit of claim 15 , wherein the clock generation circuit comprises an injection-locked oscillator (ILO) configured to generate a reference clock signal, the reference clock signal being provided to the differential input as the differential clock signals.
18 . The driver circuit of claim 15 , wherein the MUX comprises a 4:1 multiplexer, the MUX being configured to combine four input data streams into a single output data stream based on the timing of the corrected differential clock signals.
19 . The driver circuit of claim 15 , further comprising a parallel-to-serial (P2S) converter coupled to the MUX.
20 . The driver circuit of claim 15 , further comprising a controller coupled to the negative output, the controller being configured to provide a control signal disengage the first crossover inverter based at least on the negative output.

Description

FIELD OF INVENTION The present invention is directed to electrical circuits. BACKGROUND OF THE INVENTION In high-speed communication systems and other digital applications, the integrity and timing of clock signals are crucial for ensuring accurate data transmission and processing. Clock signals serve as the timing reference that coordinates the sequence of operations within electronic circuits, such as data sampling, processing, and transmission. In many modern systems, data is transmitted as differential signals, where a pair of clock signals—one positive and one negative—are used to reduce noise and improve signal integrity. However, in practical implementations, clock signals are often subject to various forms of degradation as they propagate through the circuit, such as phase misalignment, inter-symbol interference, jitter, and others. To address these issues, circuits often incorporate clock signal correction mechanisms. These mechanisms adjust the timing and phase of the clock signals in real time, ensuring that the differential signals remain synchronized and that the overall system performance is maintained. By correcting phase misalignments, duty cycle distortions, and other forms of degradation, clock signal correction improves the reliability and accuracy of high-speed communication systems. In the past, various mechanisms for clock signal corrections have been proposed, but they are inadequate. Improved methods and systems are desired. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified diagram illustrating circuit 100 for adjusting differential clock signals according to embodiments of the present invention. FIG. 2 is a simplified plot illustrating pre-cursor and post-cursor correction according to embodiments of the present invention. FIG. 3 is a simplified diagram illustrating circuit 300 for providing adjusting differential clock signals according to embodiments of the present invention. FIG. 4 is a simplified diagram illustrating driver circuit 400 with clock signal correction according to embodiments of the present invention. FIG. 5 is a simplified diagram illustrating an electro-photonic network with clock signal correction according to embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to electrical circuits. In an embodiment, the present invention provides a clock compensation device configured to correct timing discrepancies in differential clock signals. The circuit comprises positive and negative lines with multiple inverters, including crossover inverters that generate correction signals to maintain synchronization between the clock signals. There are other embodiments as well. The following description is presented to enable one of ordinary skill in the art to make and use the invention and to incorporate it in the context of particular applications. Various modifications, as well as a variety of uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments presented, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention. The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification, (including any accompanying claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. Furthermore, any element in a claim that does not explicitly state “means for” performing a specified function, or “step for” performing a specific function, is not to be interpreted as a “means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6. In particular, the use of “step of” or “act of” in the Claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6. When an element is referred to herein as being “connected” or “coupled” to another element, it is to be understood that the elements can be directly connected to the ot