US-20260128858-A1 - ENCRYPTOR AND MEMORY CONTROLLER INCLUDING THE SAME

US20260128858A1US 20260128858 A1US20260128858 A1US 20260128858A1US-20260128858-A1

Abstract

An encryptor includes a first calculator, a second calculator, a third calculator and a fourth calculator. The first calculator receives plaintext data, performs an XOR operation based on one of a plurality of round key data during each round, and outputs ciphertext data. The second calculator performs a substitution operation on an output of the first calculator using an SBOX during each round. The SBOX is implemented based on a first corrected lookup table that is converted from a first standard lookup table. The third calculator performs a row transformation operation on an output of the second calculator during each round. The fourth calculator performs a column transformation operation on an output of the third calculator using the SBOX and at least one TBOX during each round. The at least one TBOX is implemented based on at least one second corrected lookup table that is converted from at least one second standard lookup table.

Inventors

Wijik LEE
Jiyoup KIM
Dongmin Shin

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250603
Priority Date: 20241105

Claims (20)

1 . A processor configured to: perform an XOR operation on plaintext data based on one of a plurality of round key data to obtain a first calculation output; perform a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; perform a row transformation operation on the second calculation output to obtain a third calculation output; perform a column transformation operation on the third calculation output using the SBOX and a transformation box (TBOX) that is implemented based on a second corrected lookup table converted from a second standard lookup table, to obtain a fourth calculation output; and obtain ciphertext data based on the third calculation output and the fourth calculation output.
2 . The processor of claim 1 , wherein the processor is further configured to: obtain the first corrected lookup table by performing the XOR operation based on the first standard lookup table, and obtain the second corrected lookup table by performing the XOR operation based on the second standard lookup table.
3 . The processor of claim 2 , wherein: the first standard lookup table comprises a plurality of first standard elements, and the first corrected lookup table comprises a plurality of first corrected elements, each of the plurality of first corrected elements is obtained by performing the XOR operation on a respective one of the plurality of first standard elements and a first value, the second standard lookup table comprises a plurality of second standard elements, and the second corrected lookup table comprises a plurality of second corrected elements, and each of the plurality of second corrected elements is obtained by performing the XOR operation on a respective one of the plurality of second standard elements and a second value.
4 . The processor of claim 3 , wherein each of the SBOX and the TBOX is implemented in hardware that comprises a plurality of logic gates.
5 . The processor of claim 4 , wherein: the first value and the second value are determined such that a logic depth of each of the SBOX and the TBOX is minimized, and the logic depth represents a maximum number of logic gates through which an input signal passes until an output signal is generated based on the input signal.
6 . The processor of claim 3 , wherein the first value is different from the second value.
7 . The processor of claim 1 , wherein: the second standard lookup table comprises a second-first standard lookup table and a second-second standard lookup table, the second corrected lookup table comprises a second-first corrected lookup table that is obtained by performing the XOR operation based on the second-first standard lookup table, and a second-second corrected lookup table that is obtained by performing the XOR operation based on the second-second standard lookup table, and the TBOX comprises a first TBOX that is implemented based on the second-first corrected lookup table, and a second TBOX that is implemented based on the second-second corrected lookup table.
8 . The processor of claim 7 , wherein: the first corrected lookup table comprises a plurality of first corrected elements, the second-first corrected lookup table comprises a plurality of second-first corrected elements, and the second-second corrected lookup table comprises a plurality of second-second corrected elements, the processor is further configured to output the fourth calculation output that comprises a plurality of elements, and one of the plurality of elements in the fourth calculation output is obtained based on two of the plurality of first corrected elements, one of the plurality of second-first corrected elements and one of the plurality of second-second corrected elements.
9 . The processor of claim 8 , wherein the processor is further configured to: perform the XOR operation based on the two of the plurality of first corrected elements, the one of the plurality of second-first corrected elements and the one of the plurality of second-second corrected elements.
10 . The processor of claim 7 , wherein: the first standard lookup table comprises a plurality of first standard elements, the second-first standard lookup table comprises a plurality of second-first standard elements, and the second-second standard lookup table comprises a plurality of second-second standard elements, each of the plurality of second-first standard elements is obtained by multiplying a respective one of the plurality of first standard elements by two, and each of the plurality of second-second standard elements is obtained by multiplying a respective one of the plurality of first standard elements by three.
11 . The processor of claim 1 , wherein: the second standard lookup table comprises a second-first standard lookup table, the second corrected lookup table comprises a second-first corrected lookup table that is obtained by performing the XOR operation based on the second-first standard lookup table, and the TBOX comprises a first TBOX that is implemented based on the second-first corrected lookup table.
12 . The processor of claim 11 , wherein: the first corrected lookup table comprises a plurality of first corrected elements, and the second-first corrected lookup table comprises a plurality of second-first corrected elements, the processor is further configured to output the fourth calculation output that comprises a plurality of elements, and one of the plurality of elements in the fourth calculation output is obtained based on three of the plurality of first corrected elements and two of the plurality of second-first corrected elements.
13 . The processor of claim 1 , wherein the ciphertext data is obtained through a plurality of operation rounds: the plurality of operation rounds comprises an initial round and first to Nth rounds, where N is a positive integer greater than or equal to two, and the plurality of round key data comprises initial round key data and first to Nth round key data.
14 . The processor of claim 13 , wherein, during the initial round, the processor is further configured to perform the XOR operation on the plaintext data and the initial round key data.
15 . The processor of claim 14 , wherein M is a positive integer greater than or equal to one and smaller than or equal to (N−1), and during an Mth round among the first to Nth rounds, the processor is further configured to: perform the substitution operation on the first calculation output using the SBOX; perform the row transformation operation on the second calculation output; perform the column transformation operation on the third calculation output using the SBOX and the TBOX to obtain the fourth calculation output; and perform the XOR operation on the fourth calculation output and Mth round key data.
16 . The processor of claim 15 , wherein, during the Nth round, the processor is further configured to: perform the substitution operation on the first calculation output using the SBOX, perform the row transformation operation on the second calculation output, and generate the ciphertext data by performing the XOR operation on the third calculation output and the Nth round key data.
17 . A memory controller comprising: a processor; and a buffer memory configured to temporarily store data that is processed by the processor; wherein the processor is configured to perform an encryption operation to: perform an XOR operation on first data based on one of a plurality of round key data to obtain a first calculation output; perform a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; perform a row transformation operation on the second calculator output to obtain a third calculation output; perform a column transformation operation on the third calculation output using the SBOX and a transformation box (TBOX) that is implemented based on second corrected lookup table converted from second standard lookup table, to obtain a fourth calculation output; and obtain ciphertext data based on the third calculation output and the fourth calculation output.
18 . The memory controller of claim 17 , wherein the processor is further configured to: perform a decryption operation on second data that is received from the buffer memory.
19 . The memory controller of claim 18 , wherein the processor is further configured to perform the encryption operation and the decryption operation that are implemented based on advanced encryption standard (AES) standard.
20 . An encryption method performed by at least one processor, the encryption method comprising: performing an XOR operation on plaintext data based on one of a plurality of round key data to obtain a first calculation output; performing a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; performing a row transformation operation on the second calculation output to obtain a third calculation output; performing a column transformation operation on the third calculation output using the SBOX and a transformation box (TBOX) that is implemented based on a second corrected lookup table converted from a second standard lookup table, to obtain a fourth calculation output; and obtaining ciphertext data based on the third calculation output and the fourth calculation output.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2024-0155052 filed on Nov. 5, 2024 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety. BACKGROUND 1. Field Example embodiments relate generally to semiconductor integrated circuits, and more particularly to encryptors and memory controllers including the encryptors. 2. Description of the Related Art An encryption technique is commonly used to ensure the security of data transmission. In the encryption technique, a plaintext may be encrypted at a transmission side, while ciphertext may be decrypted at a reception side. The process of encrypting plaintext and decrypting ciphertext may be collectively referred to as the encryption technique. Since encryption operations are usually slow, an encryptor may be implemented as hardware to be applied to a device, such as smart cards. For example, various encryption algorithms, such as a data encryption standard (DES), an advanced encryption standard (AES), an ARIA standard, may be used. SUMMARY At least one example embodiment of the present disclosure provides an encryptor capable of having low latency and high throughput characteristics and performing high-speed operations. At least one example embodiment of the present disclosure provides a memory controller including the encryptor. According to an aspect of the disclosure, a processor may perform an XOR operation on plaintext data based on one of a plurality of round key data to obtain a first calculation output; perform a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; perform a row transformation operation on the second calculation output to obtain a third calculation output; perform a column transformation operation on the third calculation output using the SBOX and a transformation box (TBOX) that is implemented based on a second corrected lookup table converted from a second standard lookup table, to obtain a fourth calculation output; and obtain ciphertext data based on the third calculation output and the fourth calculation output. According to another aspect of the disclosure, a memory controller may include: a processor; and a buffer memory configured to temporarily store data that is processed by the processor; wherein the processor is configured to perform an encryption operation to: perform an XOR operation on first data based on one of a plurality of round key data to obtain a first calculation output; perform a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; perform a row transformation operation on the second calculator output to obtain a third calculation output; perform a column transformation operation on the third calculation output using the SBOX and transformation box (TBOX) that is implemented based on second corrected lookup table converted from second standard lookup table, to obtain a fourth calculation output; and obtain ciphertext data based on the third calculation output and the fourth calculation output. According to an aspect of the disclosure, an encryption method performed by at least one processor, may include: performing an XOR operation on plaintext data based on one of a plurality of round key data to obtain a first calculation output; performing a substitution operation on the first calculation output using a substitution box (SBOX) that is implemented based on a first corrected lookup table converted from a first standard lookup table, to obtain a second calculation output; performing a row transformation operation on the second calculation output to obtain a third calculation output; performing a column transformation operation on the third calculation output using the SBOX and a transformation box (TBOX) that is implemented based on a second corrected lookup table converted from a second standard lookup table, to obtain a fourth calculation output; and obtaining ciphertext data based on the third calculation output and the fourth calculation output. According to example embodiments, an encryptor generates ciphertext data by performing a plurality of rounds based on plaintext data, and includes a first calculator, a second calculator, a third calculator and a fourth calculator. The first calculator receives the plaintext data, performs an XOR operation based on one of a plurality of round key data during each round, and outputs the ciphertext data. The second calculator performs a substitution operation on an output of the first calculator using a substitution box (SBOX) during each round. The SBOX is implemented