US-20260128932-A1 - TRANSLATION DEVICE

US20260128932A1US 20260128932 A1US20260128932 A1US 20260128932A1US-20260128932-A1

Abstract

A translation device includes a first input/output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a non-return to zero (NRZ) method through a plurality of first pins; a second input/output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a pulse amplitude modulation- 3 (PAM- 3 ) method through a plurality of second pins; and a translation circuit configured to translate the first signal to the second signal, or translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed.

Inventors

Jaehyun BAEK
HYOUNGWOOK KIM
Sungchul Chun

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260507
Application Date: 20250623
Priority Date: 20241107

Claims (20)

1 . A translation device, comprising: a first input/output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a non-return to zero (NRZ) method through a plurality of first pins; a second input/output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a pulse amplitude modulation- 3 (PAM-3) method through a plurality of second pins; and a translation circuit configured to translate the first signal to the second signal or translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed.
2 . The translation device of claim 1 , wherein the first signal includes a first clock signal, a first command/address signal, and a first data signal, wherein the plurality of first pins include a first clock pin, a plurality of first command/address pins, and a plurality of first data pins, wherein the first clock signal is received through the first clock pin, the first command/address signal is received through the plurality of first command/address pins, and the first data signal is transmitted and received through the plurality of first data pins, and wherein a number of the first command/address pins is less than a number of the first data pins.
3 . The translation device of claim 2 , wherein the second signal includes a second clock signal, a second command/address signal, and a second data signal, wherein the plurality of second pins includes a second clock pin, a second command/address pin, and a second data pin, and wherein the second clock signal is transmitted through the second clock pin, the second command/address signal is transmitted through the second command/address pin, and the second data signal is transmitted and received through the second data pin.
4 . The translation device of claim 3 , wherein a number of the plurality of first pins is greater than a number of the plurality of second pins.
5 . The translation device of claim 3 , further comprising: a phase locked loop (PLL) circuit configured to multiply and output the first clock signal and the second clock signal, wherein the translation circuit is configured to translate the first signal having the first signal speed into the second signal having the second signal speed, or the second signal having the second signal speed into the first signal having the first signal speed.
6 . The translation device of claim 5 , further comprising: a mode register configured to store information about the first signal speed, the second signal speed, the number of the plurality of first pins, and the number of the plurality of second pins; and a command generator configured to output the first command/address signal as the second command/address signal according to a multiplied first clock signal.
7 . The translation device of claim 5 , wherein the translation circuit is configured to translate at least two bits of the first signal into at least one symbol of the second signal, and translate at least one symbol among a plurality of symbols of the second signal into at least two bits of the first signal.
8 . The translation device of claim 7 , wherein the translation circuit is configured to translate 11 bits of the first signal into 7 symbols of the second signal, and 7 symbols of the second signal into 11 bits of the first signal.
9 . A translation device, comprising: a first input/output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a NRZ method, the first signal including a first clock signal, a first command/address signal, and a first data signal; a second input/output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a PAM-3 method, the second signal including a second clock signal, a second command/address signal, and a second data signal; a phase locked loop (PLL) circuit configured to multiply the first clock signal and output the multiplied first clock signal; a command generator configured to output the first command/address signal as the second command/address signal according to the multiplied first clock signal; and a translation circuit configured to translate the first data signal to the second data signal or to translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed, and wherein the translation circuit is configured to translate at least two bits among a plurality of bits included in the first data signal to at least one symbol included in the second data signal, or translate at least one symbol among a plurality of symbols of the second signal to at least two bits of the first signal.
10 . The translation device of claim 9 , wherein the first signal further includes a first on the fly (OTF) signal.
11 . The translation device of claim 10 , wherein the translation circuit is configured to: copy the first data signal using the first OTF signal and generate a copied first data signal, and combine the first data signal and the copied first data signal and translate a combined signal into the second data signal.
12 . The translation device of claim 11 , wherein the translation circuit is configured to translate the second data signal to the first data signal and the copied first data signal.
13 . The translation device of claim 10 , wherein the first command/address signal includes a 1 - 1 command/address signal, and a 1 - 2 command/address signal different from the 1 - 1 command/address signal, and wherein the first data signal includes a 1 - 1 data signal and a 1 - 2 data signal different from the 1 - 1 data signal.
14 . The translation device of claim 13 , wherein the translation circuit is configured to: combine the 1 - 1 command/address signal and the 1 - 2 command/address signal and translate a combined signal to a second command/address signal, and combine the 1 - 1 data signal and the 1 - 2 data signal and translate the combined signal to a second data signal.
15 . The translation device of claim 14 , wherein the translation circuit is configured to: translate the second command/address signal to the 1 - 1 command/address signal and the 1 - 2 command/address signal, and translate the second data signal to the 1 - 1 data signal and the 1 - 2 data signal.
16 . The translation device of claim 13 , wherein the first signal further includes the first OTF signal and a second OTF signal.
17 . The translation device of claim 16 , wherein the translation circuit is configured to: copy the 1 - 1 data signal using the first OTF signal and generate a copied 1 - 1 data signal, and copy the 1 - 2 data signal using the second OTF signal and generate a copied 1 - 2 data signal.
18 . The translation device of claim 17 , wherein the translation circuit is configured to: combine the 1 - 1 data signal, the 1 - 2 data signal, the copied 1 - 1 data signal, and the copied 1 - 2 data signal, and translate a combined signal to the second data signal.
19 . A translation device, comprising: a first input/output circuit configured to transmit and receive a first clock signal, a first command/address signal, and a first data signal, wherein each of the first clock signal, the first command/address signal and the first data signal is a signal having a first signal speed modulated based on a NRZ method through a plurality of first pins; a second input/output circuit configured to transmit and receive a second clock signal, a second command/address signal, and a second data signal, wherein each of the second clock signal, the second command/address signal, and the second data signal is a signal having a second signal speed modulated based on a PAM-3 method through a plurality of second pins; a translation circuit configured to translate the first data signal to the second data signal, or translate the second data signal to the first data signal; a PLL circuit configured to multiply and output the first clock signal having the first signal speed; a command generator configured to output the first command/address signal as the second command/address signal according to a multiplied first clock signal; a mode register configured to store information about the first signal speed and the second signal speed; a first training circuit configured to control an input time of at least one of: the first data signal, the first clock signal, or the first command/address signal; and a second training circuit configured to control an input time of at least one of: the second data signal, the second clock signal, or the second command/address signal.
20 . The translation device of claim 19 , further comprising: a comparator configured to compare a signal obtained by translating the first data signal to the second signal speed by the translation circuit with a signal before translating the first data signal to the first signal speed by the translation circuit.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims benefit of priority to Korean Patent Application No. 10-2024-0157144, filed on Nov. 7, 2024 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. FIELD Example embodiments of the present disclosure relate to a translation device. BACKGROUND A memory device may receive a clock signal, a command/address signal, and a data signal from an external device. A multilevel signaling method may be required to improve efficiency of an input/output interface of a memory device. In this case, a method of improving efficiency of the input/output interface of the memory device based on a signal according to the pulse amplitude modulation-3 (PAM-3) method having three voltage levels may be suggested. In mass production of a memory device, a memory device may be tested as a device under test (DUT). The test device may use non-return to zero (NRZ) having two voltage levels as an interface of a general digital circuit. Accordingly, in a test of a memory device based on a PAM-3 method, issues such as developing a new test device or replacing major components related to signal generation in an existing translation device may occur. SUMMARY An example embodiment of the present disclosure is to provide a translation device which may translate different signal methods and signal speeds such that a test device using a low-speed NRZ interface may perform a test on a memory device using a high-speed PAM-3 interface. According to an example embodiment of the present disclosure, a translation device includes a first input/output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a non-return to zero (NRZ) method through a plurality of first pins; a second input/output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a pulse amplitude modulation-3 (PAM-3) method through a plurality of second pins; and a translation circuit configured to translate the first signal to the second signal or translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first speed. According to an example embodiment of the present disclosure, a translation device includes a first input/output circuit configured to transmit and receive a first signal having a first signal speed modulated based on a NRZ method, the first signal including a first clock signal, a first command/address signal, and a first data signal; a second input/output circuit configured to transmit and receive a second signal having a second signal speed modulated based on a PAM-3 method, the second signal including a second clock signal, a second command/address signal, and a second data signal; a phase locked loop (PLL) circuit configured to multiply the first clock signal and output the multiplied first clock signal; a command generator configured to output the first command/address signal as the second command/address signal according to the multiplied first clock signal; and a translation circuit configured to translate the first data signal to the second data signal or to translate the second signal to the first signal, wherein the second signal speed is equal to or greater than the first signal speed, and wherein the translation circuit is configured to translate at least two bits among a plurality of bits included in the first data signal to at least one symbol included in the second data signal, or translate at least one symbol among a plurality of symbols of the second signal to at least two bits of the first signal. According to an example embodiment of the present disclosure, a translation device includes a first input/output circuit configured to transmit and receive a first clock signal, a first command/address signal, and a first data signal, wherein each of the first clock signal, the first command/address signal and the first data signal is a signal having a first signal speed modulated based on a NRZ method through a plurality of first pins; a second input/output circuit configured to transmit and receive a second clock signal, a second command/address signal, and a second data signal, wherein each of the second clock signal, the second command/address signal and the second data signal is a signal having a second signal speed modulated based on a PAM-3 method through a plurality of second pins; a translation circuit configured to translate the first data signal to the second data signal or translate the second data signal to the first data signal; a PLL circuit configured to multiply and output the first clock signal having the first signal speed; a command generator configured to output the first command/address signal as the second command/address signal according to a multiplied first clock signal; a mode register configured to store information about the first signal speed and the